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STPIC6A259M PDF预览

STPIC6A259M

更新时间: 2024-11-27 22:28:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管信息通信管理双倍数据速率
页数 文件大小 规格书
13页 389K
描述
POWER LOGIC 8-BIT ADDRESSABLE LATCH

STPIC6A259M 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:BATWING, SO-24
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:NJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:15.4 mm
负载电容(CL):30 pF逻辑集成电路类型:D FLIP-FLOP
位数:1功能数量:1
端子数量:24最高工作温度:125 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:LOW LEVEL
宽度:7.5 mmBase Number Matches:1

STPIC6A259M 数据手册

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STPIC6A259  
POWER LOGIC 8-BIT ADDRESSABLE LATCH  
PRELIMINARY DATA  
LOW R  
: 1TYP  
DS(on)  
OUTPUT SHORT-CIRCUIT PROTECTION  
75mJ AVAILANCHE ENERGY  
EIGHT 350mA DMOS OUTPUTS  
50V SWITCHING CAPABILITY  
FOUR DISTINCT FUNCTION MODES  
LOW POWER CONSUMPTION  
DESCRIPTION  
SOP  
This power logic 8-bit addressable latch controls  
open-drain DMOS transistor outputs and is  
designed  
for  
general-purpose  
storage  
applications in digital systems. Specific uses  
include working registers, serial-holding registers,  
and decoders or demultiplexers. This is a  
multifunctional device capable of operating as  
eight addressable latches or an 8-line  
demultiplexer with active-low DMOS outputs.  
Each open-drain DMOS transistor features an  
independent chopping current-limiting circuit to  
prevent damage in the case of a short circuit.  
Four distinct modes of operation are selectable by  
controlling the clear (CLR) and enable (G) inputs  
and enumerated in the function table. In the  
addressable-latch mode, data at the data-in (D)  
terminal is written into the addressed latch. The  
addressed DMOS-transistor output inverts the  
data input with all unadressed DMOS-transistor  
output remaining in their previuous state. In the  
MOS-transistor outputs remain in their previous  
states and are unaffected by the data or address  
inputs. To eliminate the possibility of entering  
erroneus data in the latch, enable G should be  
held high (inactive) while the address lines are  
changing. In the 8-line demoultiplexing mode, the  
addressed output is inverted with respectto the D  
input and all other output are high. In the clear  
mode, all outputs are high and unaffected by the  
address and data inputs.  
Separate power ground (PGND) and logic ground  
(LGND) terminals are providied to facilitate  
maximum system flexibility. All PGND terminals  
are interally connected, and each pGND terminal  
must be externally connected to the power system  
ground in order to minimize parasitic impedance.  
A single-point connection between LGND and  
PGND must be made externally in a manner that  
reduces crosstalk between the logi and load  
circuits.  
The STPIC6A259 is offered in  
a termally  
enhanced SO-24 package. The STPIC6A259 is  
characterized for operation over the operating  
case temperature range -40°C to 125°C.  
ORDERING CODES  
Type  
Package  
SO-24 Batwing (Tube)  
SO-24 Batwing (Tape & Reel)  
Comments  
STPIC6A259M  
50parts per tube / 20tube per box  
2500 parts per reel  
STPIC6A259MTR  
March 2001  
1/13  
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.  

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