STPIC6A259

更新时间： 2024-11-27 22:28:15

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		锁存器双倍数据速率
页数	文件大小	规格书
13页	389K
描述
POWER LOGIC 8-BIT ADDRESSABLE LATCH

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中文翻译

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数据手册

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STPIC6A259 数据手册

STPIC6A259

POWER LOGIC 8-BIT ADDRESSABLE LATCH

PRELIMINARY DATA

■

LOW R

: 1Ω TYP

DS(on)

OUTPUT SHORT-CIRCUIT PROTECTION

75mJ AVAILANCHE ENERGY

EIGHT 350mA DMOS OUTPUTS

50V SWITCHING CAPABILITY

FOUR DISTINCT FUNCTION MODES

LOW POWER CONSUMPTION

DESCRIPTION

SOP

This power logic 8-bit addressable latch controls

open-drain DMOS transistor outputs and is

designed

for

general-purpose

storage

applications in digital systems. Specific uses

include working registers, serial-holding registers,

and decoders or demultiplexers. This is a

multifunctional device capable of operating as

eight addressable latches or an 8-line

demultiplexer with active-low DMOS outputs.

Each open-drain DMOS transistor features an

independent chopping current-limiting circuit to

prevent damage in the case of a short circuit.

Four distinct modes of operation are selectable by

controlling the clear (CLR) and enable (G) inputs

and enumerated in the function table. In the

addressable-latch mode, data at the data-in (D)

terminal is written into the addressed latch. The

addressed DMOS-transistor output inverts the

data input with all unadressed DMOS-transistor

output remaining in their previuous state. In the

MOS-transistor outputs remain in their previous

states and are unaffected by the data or address

inputs. To eliminate the possibility of entering

erroneus data in the latch, enable G should be

held high (inactive) while the address lines are

changing. In the 8-line demoultiplexing mode, the

addressed output is inverted with respectto the D

input and all other output are high. In the clear

mode, all outputs are high and unaffected by the

address and data inputs.

Separate power ground (PGND) and logic ground

(LGND) terminals are providied to facilitate

maximum system flexibility. All PGND terminals

are interally connected, and each pGND terminal

must be externally connected to the power system

ground in order to minimize parasitic impedance.

A single-point connection between LGND and

PGND must be made externally in a manner that

reduces crosstalk between the logi and load

circuits.

The STPIC6A259 is offered in

a termally

enhanced SO-24 package. The STPIC6A259 is

characterized for operation over the operating

case temperature range -40°C to 125°C.

ORDERING CODES

Type

Package

SO-24 Batwing (Tube)

SO-24 Batwing (Tape & Reel)

Comments

STPIC6A259M

50parts per tube / 20tube per box

2500 parts per reel

STPIC6A259MTR

March 2001

1/13

This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.

12 3 4 5 6 7...13

中文翻译

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与STPIC6A259相关器件

型号	品牌	获取价格	描述	数据表
STPIC6A259M	STMICROELECTRONICS	获取价格	POWER LOGIC 8-BIT ADDRESSABLE LATCH
STPIC6A259MTR	STMICROELECTRONICS	获取价格	POWER LOGIC 8-BIT ADDRESSABLE LATCH
STPIC6C595	STMICROELECTRONICS	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER
STPIC6C595_08	STMICROELECTRONICS	获取价格	Power logic 8-bit shift register
STPIC6C595M	STMICROELECTRONICS	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER
STPIC6C595MTR	STMICROELECTRONICS	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER
STPIC6C595TTR	STMICROELECTRONICS	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER
STPIC6D595	STMICROELECTRONICS	获取价格	Power logic 8-bit shift register
STPIC6D595B1	STMICROELECTRONICS	获取价格	Power logic 8-bit shift register
STPIC6D595M	STMICROELECTRONICS	获取价格	Power logic 8-bit shift register

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