STM8S105xx
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,
integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C
Interrupt management
Nested interrupt controller with 32 interrupts
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Up to 37 external interrupts on 6 vectors
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Timers
LQFP48 7x7
LQFP44 10x10
UFQFPN32 5x5
LQFP32 7x7
2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
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Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
SDIP32 400 ml
VFQFPN32 5x5
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
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Features
Core
Window and independent watchdog timers
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Communications interfaces
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UART with clock output for synchronous
operation, Smartcard, IrDA, LIN
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Extended instruction set
SPI interface up to 8 Mbit/s
I2C interface up to 400 Kbit/s
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Memories
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Medium-density Flash/EEPROM:
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Program memory up to 32 Kbytes; data
retention 20 years at 55°C after 10 kcycles
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Analog-to-digital converter (ADC)
10-bit, ±1 LSB ADC with up to 10 multiplexed
channels, scan mode and analog watchdog
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Data memory up to 1 Kbytes true data
EEPROM; endurance 300 kcycles
I/Os
RAM: Up to 2 Kbytes
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Up to 38 I/Os on a 48-pin package including 16
high sink outputs
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Clock, reset and supply management
Highly robust I/O design, immune against current
injection
2.95 V to 5.5 V operating voltage
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Flexible clock control, 4 master clock sources:
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Low power crystal resonator oscillator
Development support
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Embedded single wire interface module (SWIM)
for fast on-chip programming and non intrusive
debugging
External clock input
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Internal, user-trimmable 16 MHz RC
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Internal low power 128 kHz RC
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Unique ID
Clock security system with clock monitor
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96-bit unique key for each device
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Power management:
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Table 1: Device summary
Low power modes (wait, active-halt, halt)
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Reference
Part number
Switch-off peripheral clocks individually
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STM8S105xx
STM8S105K4, STM8S105K6, STM8S105S4, STM8S105S6,
STM8S105C4, STM8S105C6
Permanently active, low consumption power-on
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and power-down reset
April 2010
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DocID14771 Rev 9
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