STM32L100x6/8/B-A
Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3,
128KB Flash, 16KB SRAM, 2KB EEPROM, LCD, USB, ADC, DAC
Datasheet - production data
Features
• Ultra-low-power platform
UFQFPN48
7 × 7 mm
LQFP64 10 × 10 mm
– 1.8 V to 3.6 V power supply
– -40°C to 85°C temperature range
– 0.28 µA Standby mode (2 wakeup pins)
– 1.11 µA Standby mode + RTC
– 0.44 µA Stop mode (16 wakeup lines)
– 1.38 µA Stop mode + RTC
• Memories
– Up to 128 Kbytes Flash memory with ECC
– Up to 16 Kbytes RAM
– Up to 2Kbytes of true EEPROM with ECC
– 20 byte backup register
– 10.9 µA Low-power Run mode
– 185 µA/MHz Run mode
• LCD Driver for up to 8x28 segments
– Support contrast adjustment
– Support blinking mode
– 10 nA ultra-low I/O leakage
– < 8 µs wakeup time
®
®
– Step-up converter on board
• Core: ARM Cortex -M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 1.25 DMIPS/MHz (Dhrystone 2.1)
– Memory protection unit
• Rich analog peripherals (down to 1.8 V)
– 12-bit ADC 1 Msps up to 24 channels
– 12-bit DAC 2 channels with output buffers
– 2x ultra-low-power comparators
(window mode and wakeup capability)
• Reset and supply management
– Ultra-safe, low-power BOR (brownout
reset) with 5 selectable thresholds
• DMA controller 7x channels
– Ultra-low-power POR/PDR
• 8x peripheral communication interfaces
– 1x USB 2.0 (internal 48 MHz PLL)
– 3x USART (ISO 7816, IrDA)
– 2x SPI 16 Mbit/s
– Programmable voltage detector (PVD)
• Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– High Speed Internal 16 MHz
– Internal low-power 37 kHz RC
– 2x I2C (SMBus/PMBus)
• 10x timers: 6x 16-bit with up to 4 IC/OC/PWM
channels, 2x 16-bit basic timers, 2x watchdog
timers (independent and window)
– Internal multispeed low-power 65 kHz to
4.2 MHz
• CRC calculation unit
– PLL for CPU clock and USB (48 MHz)
Table 1. Device summary
• Pre-programmed bootloader
– USART supported
Reference
Part number
• Development support
STM32L100C6xxA,
STM32L100R8xxA,
STM32L100RBxxA
STM32L100C6-A,
STM32L100R8-A,
STM32L100RB-A
– Serial wire debug supported
– JTAG and trace supported
• Up to 51 fast I/Os (42 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
April 2016
DocID025966 Rev 5
1/102
This is information on a product in full production.
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