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STM32G031F4M3TR

更新时间： 2024-11-07 02:26:03
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
117页 1931K
描述
Arm® Cortex®-M0 32-bit MCU, up to 64 KB Flash, 8 KB RAM, 2x USART, timers, ADC, comm. I/Fs, 1.7-3.6V

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STM32G031F4M3TR 数据手册

 浏览型号STM32G031F4M3TR的Datasheet PDF文件第2页浏览型号STM32G031F4M3TR的Datasheet PDF文件第3页浏览型号STM32G031F4M3TR的Datasheet PDF文件第4页浏览型号STM32G031F4M3TR的Datasheet PDF文件第5页浏览型号STM32G031F4M3TR的Datasheet PDF文件第6页浏览型号STM32G031F4M3TR的Datasheet PDF文件第7页 
STM32G031x4/x6/x8  
Arm® Cortex®-M0+ 32-bit MCU, up to 64 KB Flash, 8 KB RAM,  
2x USART, timers, ADC, comm. I/Fs, 1.7-3.6V  
Datasheet - production data  
Features  
®
®
• Core: Arm 32-bit Cortex -M0+ CPU,  
frequency up to 64 MHz  
SO8N  
TSSOP20  
6.4 4.4 mm  
LQFP32  
7 mm  
LQFP48  
7 mm  
UFQFPN28  
4 × 4 mm  
UFQFPN32  
5 × 5 mm  
• -40°C to 85°C/105°C/125°C operating  
4.9  
×
6 mm  
×
7
×
temperature  
7
×
• Memories  
UFQFPN48  
7 × 7 mm  
– Up to 64 Kbytes of Flash memory with  
protection and securable area  
WLCSP18  
1.86 × 2.14 mm  
– 8 Kbytes of SRAM with HW parity check  
• Communication interfaces  
• CRC calculation unit  
2
– Two I C-bus interfaces supporting Fast-  
mode Plus (1 Mbit/s) with extra current  
sink, one supporting SMBus/PMBus and  
wakeup from Stop mode  
• Reset and power management  
– Voltage range: 1.7 V to 3.6 V  
– Power-on/Power-down reset (POR/PDR)  
– Programmable Brownout reset (BOR)  
– Programmable voltage detector (PVD)  
– Two USARTs with master/slave  
synchronous SPI; one supporting ISO7816  
interface, LIN, IrDA capability, auto baud  
rate detection and wakeup feature  
– Low-power modes:  
Sleep, Stop, Standby, Shutdown  
– One low-power UART  
– V  
supply for RTC and backup registers  
BAT  
– Two SPIs (32 Mbit/s) with 4- to 16-bit  
programmable bitframe, one multiplexed  
• Clock management  
2
– 4 to 48 MHz crystal oscillator  
with I S interface  
– 32 kHz crystal oscillator with calibration  
– Internal 16 MHz RC with PLL option (±1 %)  
– Internal 32 kHz RC oscillator (±5 %)  
• Development support: serial wire debug (SWD)  
• 96-bit unique ID  
• All packages ECOPACK 2 compliant  
• Up to 44 fast I/Os  
– All mappable on external interrupt vectors  
Table 1. Device summary  
– Multiple 5 V-tolerant I/Os  
Reference  
Part number  
• 5-channel DMA controller with flexible mapping  
STM32G031C4, STM32G031F4,  
STM32G031G4, STM32G031K4,  
STM32G031J4  
• 12-bit, 0.4 µs ADC (up to 16 ext. channels)  
– Up to 16-bit with hardware oversampling  
– Conversion range: 0 to 3.6V  
STM32G031x4  
STM32G031C6, STM32G031F6,  
STM32G031G6, STM32G031K6,  
STM32G031J6  
STM32G031x6  
STM32G031x8  
• 11 timers (one 128 MHz capable): 16-bit for  
advanced motor control, one 32-bit and four  
16-bit general-purpose, two low-power 16-bit,  
two watchdogs, SysTick timer  
STM32G031C8, STM32G031F8,  
STM32G031G8, STM32G031K8,  
STM32G031Y8  
• Calendar RTC with alarm and periodic wakeup  
from Stop/Standby/Shutdown  
April 2020  
DS12992 Rev 2  
1/117  
This is information on a product in full production.  
www.st.com  
 
1234567...117

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