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STLC60133N PDF预览

STLC60133N

更新时间： 2024-09-22 13:14:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动
页数 文件大小 规格书
9页 94K
描述
SPECIALTY TELECOM CIRCUIT, PDSO28, 4 X 9 MM, HTSSOP-28

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中文翻译

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STLC60133N 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：4 X 9 MM, HTSSOP-28针数：28
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.84JESD-30 代码：R-PDSO-G28
长度：9.7 mm负电源额定电压：-6 V
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HTSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.2 mm
标称供电电压：6 V表面贴装：YES
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

STLC60133N 数据手册

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STLC60133  
XDSL LINE DRIVER  
PRELIMINARY DATA  
■
■
■
Hz  
LOW NOISE : 4nV/  
HIGH PEAK OUTPUT CURRENT: 500 mA  
HIGH SPEED  
– 140MHz Gain Bandwidth  
– 30MHz Gain Flatness  
– 400 V/us Slew Rate  
HTSSOP28  
■
LOW POWER OPERATION  
– ±5V to ±15V Voltage Supply  
– 12.5 mA/Amp (typ) Supply current  
– Power reduced Current  
ORDERING NUMBER: STLC60133  
Temperature Range: -40°C to +85°C  
■
■
■
■
LOW SINGLE TONE DISTORTION  
THERMAL AND OVERLOAD PROTECTION  
HTSSOP28 PACKAGE  
Two digital pins (PWDN0 and PWDN1) allow the driv-  
er to work in full performance mode, in low-power  
mode or two intermediate bias states.  
-40 TO +85°C OPERATING RANGE  
The low-power mode biases the output stage in order  
to provide a low impedance at the amplifier outputs  
for back termination.  
DESCRIPTION  
The STLC60133 is designed optimizing bandwidth  
and distortion performances. For proper device oper-  
ating it is necessary to work with a gain level greater  
than 15.6dB.  
The STLC60133 is a dual amplifier featuring a high  
slew rate and a large bandwidth optimized for XDSL  
applications. The device is available in a HTSSOP 28  
pin package (4x9 mm) with an exposed leadframe.  
Typical differential gain is normally +27dB, while typ-  
ical common mode gain is 15.6dB  
Thanks to its small package this line driver is suitable  
for high density ADSL line card.  
Figure 1. BLOCK DIAGRAM  
-VS +VS  
Op1  
-
IN1N  
IN1P  
OUT1  
+
PWDN0  
PWDN1  
LOGIC  
TH DETCT.  
BIAS  
DGND  
-
IN2N  
IN2P  
OUT2  
+
Op2  
D00TL462A  
October 2001  
1/9  
This is preliminary information on a new product now in development. Details are subject to change without notice.  
1234567...9

中文翻译

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