Datasheet > STL7NM60N

STL7NM60N

更新时间： 2024-11-27 12:01:31

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		栅极
页数	文件大小	规格书
13页	786K
描述
Low input capacitance and gate charge, Low gate input resistance

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STL7NM60N 数据手册

STL7NM60N

N-channel 600 V, 0.805 Ω, 5.8 A PowerFLAT™ 5x5

MDmesh™ II Power MOSFET

Features

V_{DSS @}

T_JMAX

R_DS(on)

max.

Order code

I_D

STL7NM60N

650 V

< 0.90 Ω

5.8 A⁽¹⁾

1. The value is rated according Rthj-case

■ 100% avalanche tested

■ Low input capacitance and gate charge

■ Low gate input resistance

PowerFLAT™ 5x5

Application

■ Switching applications

Description

Figure 1.

Internal schematic diagram

This device is an N-channel Power MOSFET

developed using the second generation of

MDmesh™ technology. This revolutionary Power

MOSFET associates a vertical structure to the

company’s strip layout to yield one of the world’s

lowest on-resistance and gate charge. It is

therefore suitable for the most demanding high

efficiency converters.

11 G

10 S

9 S

Pin 1

(not connected)

S 2

S 3

S 4

Drain

8 S

Top view

Table 1.

Order code

STL7NM60N

Device summary

Marking

Package

Packaging

Tape and reel

7NM60N

PowerFLAT™ 5x5

November 2011

Doc ID 18348 Rev 2

1/13

www.st.com

12 3 4 5 6 7...13

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