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STK25C48-WF35 PDF预览

STK25C48-WF35

更新时间: 2024-11-08 06:37:55
品牌 Logo 应用领域
SIMTEK 静态存储器光电二极管
页数 文件大小 规格书
10页 286K
描述
2KX8 NON-VOLATILE SRAM, 35ns, PDIP24, 0.600 INCH, PLASTIC, DIP-24

STK25C48-WF35 数据手册

 浏览型号STK25C48-WF35的Datasheet PDF文件第2页浏览型号STK25C48-WF35的Datasheet PDF文件第3页浏览型号STK25C48-WF35的Datasheet PDF文件第4页浏览型号STK25C48-WF35的Datasheet PDF文件第5页浏览型号STK25C48-WF35的Datasheet PDF文件第6页浏览型号STK25C48-WF35的Datasheet PDF文件第7页 
STK25C48  
2K x 8 AutoStore™ nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
Obsolete - Not Recommend for new Designs  
DESCRIPTION  
FEATURES  
The STK25C48 is a fast SRAM with a nonvolatile element  
incorporated in each static memory cell. The SRAM can  
be read and written an unlimited number of times, while  
independent nonvolatile data resides in the Nonvolatile  
Elements. Data transfers from the SRAM to the Nonvola-  
tile Elements (the STORE operation) can take place auto-  
matically on power down using charge stored in system  
capacitance. Transfers from the Nonvolatile Elements to  
the SRAM (the RECALL operation) take place automati-  
cally on restoration of power. The nvSRAM can be used in  
place of existing 2K x 8 SRAMs and also matches the  
pinout of 2K x 8 battery-backed SRAMs, EPROMs and  
EEPROMs, allowing direct substitution while enhancing  
performance. No support circuitry is required for micro-  
processor interfacing.  
• Nonvolatile Storage without Battery Problems  
• Directly Replaces 2K x 8 Static RAM, Battery-  
Backed RAM or EEPROMs  
• 25ns, 35ns and 45ns Access Times  
STORE to Nonvolatile Elements Initiated by  
AutoStore™ on Power Down  
RECALL to SRAM Initiated by Power Restore  
• 10mA Typical ICC at 200ns Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to Nonvolatile Ele-  
ments  
• 100-Year Data Retention over Full Industrial  
Temperature Range  
• Commercial and Industrial Temperatures  
• 24-Pin 600 PDIP Package  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
A
A
W
G
CC  
QUANTUM TRAP  
32 x 512  
2
8
VCC  
A
3
7
9
4
A
A
A
A
6
5
4
5
STORE  
A5  
A6  
A7  
A8  
A9  
STORE/  
RECALL  
CONTROL  
6
POWER  
CONTROL  
A
E
10  
STATIC RAM  
ARRAY  
7
3
2
RECALL  
8
A
DQ  
7
6
5
32 x 512  
9
A
DQ  
DQ  
DQ  
1
10  
11  
12  
A
0
DQ  
0
4
3
DQ  
DQ  
24 - 600 PDIP  
1
DQ  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
COLUMN I/O  
PIN NAMES  
COLUMN DEC  
A
- A  
10  
Address Inputs  
Write Enable  
Data In/Out  
Chip Enable  
Output Enable  
Power (+ 5V)  
Ground  
0
W
DQ - DQ  
0
7
A10  
A0 A1 A2 A3 A4  
G
E
G
E
W
V
V
CC  
SS  
March 2006  
1
Document Control # ML0005 rev 0.2  

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