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STK22C48N45I PDF预览

STK22C48N45I

更新时间: 2024-11-12 06:14:43
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
11页 298K
描述
2K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM

STK22C48N45I 数据手册

 浏览型号STK22C48N45I的Datasheet PDF文件第2页浏览型号STK22C48N45I的Datasheet PDF文件第3页浏览型号STK22C48N45I的Datasheet PDF文件第4页浏览型号STK22C48N45I的Datasheet PDF文件第5页浏览型号STK22C48N45I的Datasheet PDF文件第6页浏览型号STK22C48N45I的Datasheet PDF文件第7页 
STK22C48  
2K x 8 AutoStore™ nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
FEATURES  
DESCRIPTION  
The Simtek STK22C48 is a fast static RAM with a  
• 25ns, 35ns and 45ns Access Times  
• “Hands-off” Automatic STORE with External  
nonvolatile element incorporated in each static  
memory cell. The SRAM can be read and written an  
unlimited number of times, while independent, non-  
volatile data resides in Nonvolatile Elements. Data  
transfers from the SRAM to the Nonvolatile Elements  
(the STORE operation) can take place automatically  
on power down. A 68µF or larger capacitor tied from  
VCAP to ground guarantees the STORE operation,  
regardless of power-down slew rate or loss of power  
from “hot swapping”. Transfers from the Nonvolatile  
Elements to the SRAM (the RECALL operation) take  
place automatically on restoration of power. A hard-  
ware STORE may be initiated with the HSB pin.  
68µF Capacitor on Power Down  
STORE to Nonvolatile Elements Initiated by  
Hardware or AutoStore™ on Power Down  
• Automatic RECALL on Power Up  
• 10mA Typical ICC at 200ns Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to Nonvolatile Ele-  
ments  
• 100-Year Data Retention in Nonvolatile Ele-  
ments  
• Single 5V + 10% Operation  
• Commercial and Industrial Temperatures  
• 28-Pin DIP and SOIC Packages  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
V
V
CAP  
CCX  
V
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CAP  
NC  
CCX  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
W
A
A
A
A
A
HSB  
7
6
5
4
3
2
A
8
POWER  
Quantum Trap  
32 x 512  
A
9
CONTROL  
NC  
G
A
A
E
10  
A5  
A6  
A7  
A8  
A9  
STORE  
STORE/  
RECALL  
A
1
0
HSB  
A
DQ  
DQ  
DQ  
DQ  
DQ  
7
6
5
4
3
STATIC RAM  
CONTROL  
28 - 300 PDIP  
28 - 600 PDIP  
28 - 300 SOIC  
28 - 350 SOIC  
RECALL  
DQ  
0
1
2
ARRAY  
DQ  
32 x 512  
DQ  
V
SS  
PIN NAMES  
DQ  
DQ  
DQ  
0
1
2
COLUMN I/O  
A
- A  
Address Inputs  
Data In/Out  
0
10  
COLUMN DEC  
DQ -DQ  
0
7
DQ  
3
4
E
Chip Enable  
DQ  
W
G
HSB  
Write Enable  
Output Enable  
Hardware Store Busy (I/O)  
Power (+ 5V)  
Capacitor  
DQ  
DQ  
DQ  
5
6
7
A
A A  
A A  
1 4  
2 3  
A
10  
0
G
E
W
V
V
V
CCX  
CAP  
SS  
Ground  
December 2002  
1
Document Control # ML0004 rev 0.0  

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