Datasheet > STK17T88-WF25I

STK17T88-WF25I

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
SIMTEK		光电二极管
页数	文件大小	规格书
25页	284K
描述
REAL TIME CLOCK, PDIP40, 0.600 INCH, 0.100 INCH PITCH, ROHS COMPLIANT, PLASTIC, DIP-40

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STK17T88-WF25I 数据手册

STK17T88

nvTime^TMEvent Data Recorder

32K x 8 AutoStore^TMnvSRAM

With Real-Time Clock

FEATURES

DESCRIPTION

• Data Integrity of Simtek nvSRAM Combined

with Full-Featured Real-Time Clock

o Low Power, 300 nA Max, RTC current

o Capacitor or battery backup for RTC

• Watchdog Timer

The Simtek STK17T88 combines a 256 Kbit

nonvolatile static RAM with a full-featured real-time

clock in a reliable, monolithic integrated circuit. The

embedded

nonvolatile

elements

incorporate

• Clock Alarm with programmable Interrupts

• 25ns, 35ns and 45ns Access Times

• “Hands-off” Automatic STORE on Power Down

with only a small capacitor

• STORE to QuantumTrap™ Initiated by

Software , device pin, or on Power Down

• RECALL to SRAM Initiated by Software or

Power Up

Simtek’s QuantumTrap™ technology producing the

world’s most reliable nonvolatile memory. The

SRAM can be read and written an unlimited number

of times, while independent, nonvolatile data resides

in the nonvolatile elements.

The Real-Time Clock function provides an accurate

clock with leap year tracking and a programmable,

high accuracy oscillator. The Alarm function is pro-

grammable for one-time alarms or periodic seconds,

minutes, hours, or days. There is also a programma-

ble Watchdog Timer for process control.

• Unlimited READ, WRITE and RECALL Cycles

• High-reliability

o Endurance to 1 Million Cycles

o Retention to 100 years at 125 ºC

• 5mA Typical I_CCat 200ns Cycle Time

• Single 3V +20%, -10% Operation

• SSOP and DIP Packages, (ROHS compliant)

BLOCK DIAGRAM

V_CC

V_CAP

Quantum Trap

512 X 512

V_RTCbat

V_RTCcap

POWER

A₅

A₆

A₇

A₈

CONTROL

STORE

RECALL

STORE/

RECALL

CONTROL

STATIC RAM

ARRAY

512 X 512

A₉

HSB

A₁₁

A₁₂

A₁₃

A₁₄

SOFTWARE

DETECT

A₁₃– A₀

DQ₀

DQ₁

DQ₂

DQ₃

DQ₄

DQ₅

DQ₆

DQ₇

COLUMN I/O

X₁

COLUMN DEC

RTC

X₂

INT

A₀A₁A₂A₃A₄A₁₀

A₁₄– A₀

MUX

Figure 1. Block Diagram

April 2005

Document Control #ML0024 rev 1.2

12 3 4 5 6 7...25

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