STK16C88
32K x 8 AutoStorePlus™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
DESCRIPTION
• Transparent Data Save on Power Down
• Internal Capacitor Guarantees AutoStore™
Regardless of Power-Down Slew Rate
• Nonvolatile Storage without Battery Problems
• Directly Replaces 32K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 20ns, 25ns, 35ns and 45ns Access Times
• STORE to EEPROM Initiated by Software or
AutoStorePlus™ on Power Down
• No Data Loss from Undershoot
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention over Full Industrial
Temperature Range
The STK16C88 is a fast SRAM with a nonvolatile
EEPROM element incorporated in each static mem-
ory cell. The SRAM can be read and written an
unlimited number of times, while independent non-
volatile data resides in EEPROM. Data transfers from
the SRAM to the EEPROM (the STORE operation) can
take place automatically on power down. An internal
capacitor guarantees the STORE operation regard-
less of power-down slew rate. Transfers from the
EEPROM to the SRAM (the RECALL operation) take
place automatically on restoration of power. Initia-
tion of STORE and RECALL cycles can also be con-
trolled by entering control sequences on the SRAM
inputs. The STK16C88 is pin-compatible with 32k x
8 SRAMs and battery-backed SRAMs, allowing direct
substitution while enhancing performance. The
STK14C88, which uses an external capacitor, and
the STK15C88, which uses charge stored in system
capacitance, are alternatives for systems needing
AutoStorePlus™ operation.
• Commercial and Industrial Temperatures
• 28-Pin PDIP and SOIC Packages
BLOCK DIAGRAM
PIN CONFIGURATIONS
A
A
1
28
27
26
25
24
23
22
21
20
V
CC
14
EEPROM ARRAY
2
W
12
VCC
512 x 512
3
A
A
A
7
6
5
4
3
2
13
8
A
4
A5
A6
A7
A
A
A
5
A
A
9
STORE
6
11
STORE/
RECALL
CONTROL
POWER
CONTROL
7
G
A8
A9
STATIC RAM
ARRAY
A
8
A
E
10
RECALL
9
A
A
1
10
11
12
13
14
19
18
17
16
15
DQ
DQ
DQ
DQ
DQ
A11
A12
A13
A14
512 x 512
0
7
6
DQ
0
DQ
28 - 600 PDIP
28 - 350 SOIC*
*see order info
1
2
5
INTERNAL
CAPACITOR
DQ
4
3
V
SS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
PIN NAMES
COLUMN I/O
SOFTWARE
DETECT
A0 - A13
A
- A
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
0
14
COLUMN DEC
W
DQ - DQ
0
7
A0 A1 A2 A3 A4A10
E
G
G
E
V
V
CC
W
SS
July 1999
5-65