STK16C88-3
32K x 8 AutoStorePlus™ nvSRAM
3.3V QuantumTrap™ CMOS
Nonvolatile Static RAM
Preliminary
DESCRIPTION
FEATURES
The STK16C88-3 is a fast SRAM with a nonvolatile
element incorporated in each static memory cell.
The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in Nonvolatile Elements. Data transfers from
the SRAM to the Nonvolatile Elements (the STORE
operation) can take place automatically on power
down. An internal capacitor guarantees the STORE
operation regardless of power-down slew rate.
Transfers from the Nonvolatile Elements to the
SRAM (the RECALL operation) take place automati-
cally on restoration of power. Initiation of STORE and
RECALL cycles can also be controlled by entering
control sequences on the SRAM inputs. The
STK16C88-3 is pin-compatible with 32k x 8 SRAMs
and battery-backed SRAMs, allowing direct substitu-
tion while providing superior performance. The
STK14C88-3, which uses an external capacitor, is
also available.
• Transparent Data Save on Power Down
• Internal Capacitor Guarantees AutoStore™
Regardless of Power-Down Slew Rate
• Directly Replaces 32K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 35, 45ns and 55ns Access Times
• STORE to Nonvolatile Elements Initiated by
Software or AutoStorePlus™
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments (Commercial/Industrial)
• 100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
• Single 3.3V + 0.3V Operation
• Commercial and Industrial Temperatures
• 28-Pin PDIP Package
BLOCK DIAGRAM
PIN CONFIGURATIONS
A14
A12
A7
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
QUANTUM TRAP
V
512 x 512
CC
3
4
5
6
7
8
9
A13
A8
A5
A6
A5
A9
A6
STORE
STORE/
RECALL
A4
A11
G
A10
E
A7
POWER
A3
A8
STATIC RAM
ARRAY
CONTROL
A2
CONTROL
RECALL
A9
A1
A11
A12
A13
A14
512 x 512
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
VSS
INTERNAL
28 - 600 PDIP
CAPACITOR
DQ
DQ
DQ
0
1
2
PIN NAMES
COLUMN I/O
SOFTWARE
DETECT
A
- A
13
0
A
- A
Address Inputs
COLUMN DEC
0
14
DQ
W
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 3.3V)
Ground
3
4
DQ
DQ - DQ
0
7
DQ
DQ
DQ
5
6
7
A
0
A A A
A A
1 4
2 3
10
G
E
G
E
W
V
V
CC
SS
September 2003
1
Document Control # ML0019 rev 0.1