Datasheet > STD131

STD131

更新时间： 2024-11-08 23:34:59

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STD131\|Data Sheet

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STD131 数据手册

S MSUNG

STD131

ELECTRONICS

STD131 Standard Cell

0.18um System-On-Chip ASIC

Dec 2000, V2.0

Features

SSTL2

PECL

HSTL

High speed

Devices

1.8/2.5/3.3V

- L = 0.15um, L

= 0.18um

eff

drawn

Device 1.8/2.5/3.3V

Interface

STD131

(1.8V)

- Up to 23 million gates

- Power dissipation :24nW/MHz

- Gate Delay : 48ps @ 1.8V, 1SL

- 1.8/2.5/3.3V drive and 3.3/5V tolerant I/O

- Compilable SRAM for two different application

- 1.8V and 3.3V ADC,DAC and PLLs

3.3/5.0V

Device 3.3/5.0V CMOS/

TTL

3.3/5.0V

Tolerant

Analog cores

Analog Interface

PCI

PCI-X

Hot Swap PCI

AGP

USB

- ARM920T/ARM940T, TeakLite/Teak

AGP Bus

USB Bus

PCI Bus

Description

memory containing redundancy scheme is pro-

vided as a compiler.

STD131 is one of the Samsung ASIC library,

which consists of standard cell products imple-

mented in a 0.18um technology. STD131 utilizes

six layers of interconnect metal having metal 4, 5

and 6 layer options for products. STD131 is

diverse application speciﬁc digital and analog IPs

for system-on-chip(SOC) application. Samsung

provides a full range of products to address the

challenges of producing ultra low power and high

density devices that take advantage of SOC inte-

gration.

Variety of IPs are provided in STD131 family

including

- Processor Cores :

ARM7T/ARM9T/940T/920T from ARM,

Teaklite/TEAK from DSPG

- Memories

Compiled SRAM with two different applica-

tion and repairable SRAM with redundancy.

- Analog Cores :

ADC, DAC, PLL, RAMDAC

- IO IPs

STD131 which reduced power dissipation and

system cost by merging the logic and IPs as a

whole and connecting internally from logic to

memory data bus is ideal for high-performance

products such as HDD, Network, and Display.

Samsung design methodology offers an compre-

hensive timing driven design ﬂow including auto-

mated time budgeting, tight ﬂoorplan synthesis

integration, powerful timing analysis and timing

driven layout. Its advanced characterization ﬂow

provides accurate timing data and robust delay

models for a 0.18um very deep-submicron tech-

nology. Static veriﬁcation methods such as static

timing analysis and formal equivalence checking

provide an effective veriﬁcation methodology with

a variety of simulators. Samsung DFT methodol-

ogy supports scan design, BIST and JTAG bound-

ary scan. Samsung provides a full set of test-

ready IPs with an efﬁcient core test integration

methodology.

STD131 supports up to 23 million gates counts of

logic providing 80% of usable gate. Gate delay is

30% faster than that of STD110, 0.25um library.

Logic and compiled memory density are respec-

tively 2.6 times and 3 timer denser than those of

STD110.

STD131 also supports fully user-conﬁgurable

compiled memory elements such as high-density

and low-power applications. Each element is pro-

vided as a compiler. For high-capacity memory

solution in SOC design, the repairable

Samsung ASIC

12 3 4 5 6 7...886

中文翻译

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与STD131相关器件

型号	品牌	获取价格	描述	数据表
STD134N4F7AG	STMICROELECTRONICS	获取价格	汽车级N沟道40 V、2.5 mOhm典型值、80 A STripFET F7功率MOSF
STD-13510T	VOLGEN	获取价格	ADAPTER-18W
STD-13514T	VOLGEN	获取价格	ADAPTER-18W
STD13N50DM2AG	STMICROELECTRONICS	获取价格	汽车级N沟道500 V、0.299 Ohm典型值、11 A MDmesh DM2功率MOS
STD13N60DM2	STMICROELECTRONICS	获取价格	N沟道600 V、0.310 Ohm典型值、11 A MDmesh DM2功率MOSFET
STD13N60M2	STMICROELECTRONICS	获取价格	N沟道600 V、0.35 Ohm典型值、11 A MDmesh M2功率MOSFET，D
STD13N60M6	STMICROELECTRONICS	获取价格	N-channel 600 V, 320 mOhm typ., 10 A MDmesh M6 Power MOSFET in a DPAK package
STD13N65M2	STMICROELECTRONICS	获取价格	N沟道650 V、0.37 Ohm典型值、10 A MDmesh M2功率MOSFET，D
STD13NM60N	STMICROELECTRONICS	获取价格	N-channel 600 V, 0.28 Î© typ., 11 A MDmeshâ¢
STD13NM60ND	STMICROELECTRONICS	获取价格	N-channel 600 V, 0.32 Ohm typ., 11 A FDmesh(TM) II Power MOSFET (with fast diode) in DPAK

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