Very Low Power/Voltage CMOS SRAM
32K X 8 bit
STC
STC62WV256
DESCRIPTION
FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
The STC62WV256 is a high performance , very low power CMOS
Static Random Access Memory organized as 32,768 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.01uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable (OE) and three-state output drivers.
The STC62WV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc=3.0V
The STC62WV256 is available in the DICE form, JEDEC standard 28pin
330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and 8mm x
13.4mm TSOP (normal type).
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
PKG
TYPE
(ICCSB1, Max)
Vcc=
3.0V
Vcc=
5.0V
Vcc=
3.0V
Vcc=
5.0V
Vcc=
3.0V
STC62WV256SC
STC62WV256TC
STC62WV256PC
STC62WV256JC
STC62WV256DC
STC62WV256SI
STC62WV256TI
STC62WV256PI
STC62WV256JI
STC62WV256DI
SOP-28
TSOP-28
PDIP-28
SOJ-28
0 O C to +70 O
C
2.4V ~ 5.5V
2.4V ~ 5.5V
70
70
1uA
0.2uA
0.4uA
35mA
20mA
25mA
DICE
SOP-28
TSOP-28
PDIP-28
SOJ-28
-40 O C to +85 O
C
2uA
40mA
DICE
BLOCK DIAGRAM
PIN CONFIGURATIONS
A14
A12
A7
1
28
27
26
25
24
23
VCC
WE
A13
A8
2
A5
A6
3
A6
4
A7
Address
A5
5
A9
Memory Array
A12
A14
A13
18
62WV256SC
62WV256SI
512
Row
Decoder
A4
6
A11
OE
Input
A3
7
62WV256PC 22
512 x 512
62WV256PI
62WV256JC
62WV256JI
Buffer
A2
8
21
A10
CE
A8
A9
A1
9
20
A0
10
11
12
13
14
19
18
17
16
15
DQ7
DQ6
DQ5
DQ4
DQ3
A11
DQ0
DQ1
DQ2
GND
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
8
Column I/O
Buffer
Write Driver
Sense Amp
8
8
Data
64
A10
CE
Output
Buffer
1
2
3
4
5
6
7
8
28
OE
A11
A9
27
26
25
24
23
22
21
20
19
18
17
16
15
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
Column Decoder
12
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
CE
WE
OE
STC62WV256TC
STC62WV256TI
Control
Address Input Buffer
9
10
11
12
13
14
Vdd
Gnd
A4 A3 A2 A1 A0 A10
A1
A2
STC International Limited. reserves the right to modify document contents without notice.
Revision 2.3
Jan. 2004
R0201-STC62WV256
1
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