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STC62WV1024JCG55 PDF预览

STC62WV1024JCG55

更新时间: 2024-11-25 22:13:19
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其他 - ETC 静态存储器
页数 文件大小 规格书
10页 436K
描述
VERY LOW POWER VOLTAGE CMOS SRAM

STC62WV1024JCG55 数据手册

 浏览型号STC62WV1024JCG55的Datasheet PDF文件第2页浏览型号STC62WV1024JCG55的Datasheet PDF文件第3页浏览型号STC62WV1024JCG55的Datasheet PDF文件第4页浏览型号STC62WV1024JCG55的Datasheet PDF文件第5页浏览型号STC62WV1024JCG55的Datasheet PDF文件第6页浏览型号STC62WV1024JCG55的Datasheet PDF文件第7页 
Very Low Power/Voltage CMOS SRAM  
128K X 8 bit  
STC  
STC62WV1024  
• Easy expansion with CE2, CE1, and OE options  
„ FEATURES  
• Three state outputs and TTL compatible  
• Fully static operation  
• Data retention supply voltage as low as 1.5V  
• Wide Vcc operation voltage : 2.4V ~ 5.5V  
• Very low power consumption :  
Vcc = 3.0V C-grade : 17mA (@55ns) operating current  
I- grade : 18mA (@55ns) operating current  
C-grade : 14mA (@70ns) operating current  
I- grade : 15mA (@70ns) operating current  
0.1uA (Typ.) CMOS standby current  
Vcc = 5.0V C-grade : 46mA (55ns) operating current  
I- grade : 47mA (55ns) operating current  
C-grade : 38mA (70ns) operating current  
I- grade : 39mA (70ns) operating current  
0.6uA (Typ.) CMOS standby current  
• High speed access time :  
„ DESCRIPTION  
The STC62WV1024 is a high performance, very low power CMOS  
Static Random Access Memory organized as 131,072 words by 8 bits  
and operates from a wide range of 2.4V to 5.5V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current of  
0.1uA at 3V/25oC and maximum access time of 55ns at 3V/85oC.  
Easy memory expansion is provided by an active LOW chip  
enable (CE1), an active HIGH chip enable (CE2), and active LOW  
output enable (OE) and three-state output drivers.  
-55  
-70  
55ns  
70ns  
The STC62WV1024 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The STC62WV1024 is available in DICE form , JEDEC standard 32 pin  
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP,8mm x13.4  
mm STSOP and 8mmx20mm TSOP.  
• Automatic power down when chip is deselected  
„ PRODUCT FAMILY  
POWER DISSIPATION  
SPEED  
(ns)  
55ns : 3.0~5.5V  
70ns : 2.7~5.5V  
PRODUCT  
FAMILY  
OPERATING  
TEMPERATURE  
Vcc  
RANGE  
Operating  
STANDBY  
(ICCSB1, Max)  
PKG TYPE  
(ICC, Max)  
Vcc=3V  
Vcc=5V  
Vcc=5.0V Vcc=3.0V  
70ns  
70ns  
STC62WV1024SC  
STC62WV1024TC  
STC62WV1024STC  
STC62WV1024PC  
STC62WV1024JC  
STC62WV1024DC  
STC62WV1024SI  
STC62WV1024TI  
STC62WV1024STI  
STC62WV1024PI  
STC62WV1024JI  
STC62WV1024DI  
SOP-32  
TSOP-32  
STSOP-32  
PDIP-32  
SOJ-32  
+0 O C to +70 O  
C
C
2.4V ~ 5.5V  
2.4V ~ 5.5V  
55/70  
55/70  
38mA  
39mA  
8.0uA  
20uA  
1.3uA  
2.5uA  
14mA  
DICE  
SOP-32  
TSOP-32  
STSOP-32  
PDIP-32  
SOJ-32  
-40 O C to +85 O  
15mA  
DICE  
„ BLOCK DIAGRAM  
„ PIN CONFIGURATIONS  
NC  
A16  
A14  
A12  
A7  
1
VCC  
32  
2
A15  
CE2  
WE  
A13  
A8  
31  
A6  
A7  
A12  
A14  
A16  
A15  
A13  
A8  
3
30  
4
29  
Address  
5
28  
27  
Memory Array  
20  
1024  
Row  
Decoder  
A6  
6
Input  
A5  
7
A9  
62WV1024SC 26  
1024 x 1024  
A4  
8
62WV1024SI  
62WV1024PC  
62WV1024PI  
62WV1024JC  
62WV1024JI  
A11  
OE  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Buffer  
A3  
9
A2  
A9  
A11  
10  
11  
12  
13  
14  
15  
16  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
A1  
A0  
1024  
DQ0  
DQ1  
DQ2  
GND  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
8
Data  
Input  
Buffer  
8
Column I/O  
Write Driver  
Sense Amp  
8
1
2
3
4
5
6
7
8
A11  
A9  
A8  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
OE  
8
Data  
Output  
Buffer  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
GND  
DQ2  
DQ1  
DQ0  
A0  
128  
A13  
WE  
CE2  
A15  
VCC  
NC  
A16  
A14  
A12  
A7  
Column Decoder  
14  
62WV1024TC  
62WV1024TC  
62WV1024TI  
62WV1024STI  
CE2  
CE1  
WE  
9
Control  
Address Input Buffer  
10  
11  
12  
13  
14  
15  
16  
OE  
Vdd  
Gnd  
A5 A4 A3 A2 A1 A0 A10  
A6  
A5  
A4  
A1  
A2  
A3  
STC International Limited. reserves the right to modify document contents without notice.  
Revision 2.1  
Jan. 2004  
STC62WV1024  
1

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