Datasheet > STC5130

STC5130

更新时间： 2024-11-26 19:32:27

品牌	Logo	应用领域
CONNOR-WINFIELD		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
48页	778K
描述
Support Circuit, 1-Func, PQFP100, ROHS COMPLIANT, TQFP-100

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中文翻译

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STC5130 数据手册

STC5130

Synchronous Clock for SETS

Data Sheet

Description

Features

Functional Specification

•

For SDH SETS

The STC5130 is an integrated single chip solution for

the synchronous clock in SDH, SONET, and

Synchronous Ethernet network elements. The device is

For SONET Stratum 3, 4E, 4 and SMC, and

Synchronous Ethernet

fully compliant with

GR1244, and GR253.

ITU-T G.813, and Telcordia

•

Complies with ITU-T G.813, Telcordia GR1244,

and GR253

Supports Master/Slave operation with the

The STC5130 accepts 12 reference inputs and gener-

ates 8 independent synchronized output clocks. Refer-

ence input frequencies are automatically detected, and

inputs are individually monitored for quality. Active refer-

ence selection may be manual or automatic. All refer-

ence switches are hitless. Synchronized outputs may be

programmed for a wide variety of SONET and SDH as

well as Synchronous Ethernet frequencies.

SyncLink^TMcross-couple data link for master/

slave redundant applications

•

Accepts 12 individual clock reference inputs

Reference clock inputs are automatically fre-

quency detected

•

Supports manual or automatic reference selec-

tion

Two independent clock generators provide the standard-

ized T0 and T4 functions. Each clock generator includes

a DPLL (Digital Phase-Locked Loop), which may oper-

ate in the Freerun, Synchronized, and Holdover modes.

Both clock generators support master/slave operation

for redundant applications. The proprietary SyncLink^TM

cross-couple data link provides master/slave phase

information and state data to ensure seamless side

switches.

T0 and T4 have independent reference lists and

priority tables for automatic reference selection

•

8 synchronized output clocks

Output/input phase skew is adjustable in slave

mode, in 0.1ns steps up to 200ns

•

Hit-less reference and master/slave switching

Phase rebuild on re-lock and reference switches

Better than 0.1 ppb holdover accuracy

A standard SPI serial bus interface or parallel bus pro-

vide access to the STC5130’s comprehensive, yet sim-

ple to use internal control and status registers. The

device operates with an external OCXO or TCXO as its

MCLK at 20 MHz.

Programmable bandwidth, from 90mHz to 107Hz,

for both T0 and T4 DPLL

•

Supports SPI or parallel bus interface

IEEE 1149.1 JTAG boundary scan

Available in TQFP100 package

T0_MASTER_SLAVE

T0_XSYNC_IN

LVDS 155.52/125 MHz

Phase

Digital

Filter

Detector

19.44/38.88/51.84/77.76/25/50/125 MHz

8 kHz

2 kHz

T0 Active

Clock

Synthesizer

Ref Selector

1.544/3.088/6.176/12.352/24.704 MHz

2.048/4.096/8.192/16.384/32.768 MHz

Activity &

STC5130

Frequency

Reference Clk

Offset Monitor

44.736 MHz/34.368 MHz

T0_XSYNC_OUT

8 kHz

64 kHz

1.544 MHz

2.048 MHz

19.44 MHz

38.88 MHz

77.76 MHz

6.48 MHz

8.192 MHz

16.384 MHz

25 MHz

T4 Active

Ref Selector

1.544 MHz/2.048 MHz

T4_Xsync_Out

Phase

Digital

Filter

Clock

50 MHz

Detector

Synthesizer

T4_XSYNC_In

T4_Master_Slave

Control & Status

Registers

Serial/Parallel Bus

Interface

IEEE 1194.1

JTAG

20MHz

OCXO

TCXO

Figure 1: Functional Block Diagram

Data Sheet #: TM100

Page 1 of 48

Rev: P01

Date: 07/11/2007

Preliminary

12 3 4 5 6 7...48

中文翻译

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与STC5130相关器件

型号	品牌	获取价格	描述	数据表
STC5130-I	CONNOR-WINFIELD	获取价格	Support Circuit, 1-Func, PQFP100, ROHS COMPLIANT, TQFP-100
STC5230	CONNOR-WINFIELD	获取价格	Synchronous Clock for SETS
STC5230_15	CONNOR-WINFIELD	获取价格	Line Card Clock
STC5230-I	CONNOR-WINFIELD	获取价格	Synchronous Clock for SETS
STC53C	SUNTSU	获取价格	Ceramic SMT 4 Pad CMOS (VC)TCXO
STC53C25N07	SUNTSU	获取价格	Ceramic SMT 4 Pad CMOS (VC)TCXO
STC53C25N07E	SUNTSU	获取价格	Ceramic SMT 4 Pad CMOS (VC)TCXO
STC53C25N07F	SUNTSU	获取价格	Ceramic SMT 4 Pad CMOS (VC)TCXO
STC53C25N07G	SUNTSU	获取价格	Ceramic SMT 4 Pad CMOS (VC)TCXO
STC53C25N07V	SUNTSU	获取价格	Ceramic SMT 4 Pad CMOS (VC)TCXO

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