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STA304 PDF预览

STA304

更新时间: 2024-11-19 22:42:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 消费电路商用集成电路
页数 文件大小 规格书
30页 335K
描述
DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX⑩

STA304 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:10 X 10 MM, 1.40 MM HEIGHT, TQFP-44
针数:44Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.77
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQFP-G44JESD-609代码:e4
长度:10 mm功能数量:1
端子数量:44最高工作温度:85 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP44,.47SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Other Consumer ICs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

STA304 数据手册

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STA304  
DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™  
PRODUCT PREVIEW  
END TO END DIGITAL AUDIO INTEGRATED  
SOLUTION  
· DSP Functions:  
- DIGITAL VOLUME CONTROL  
- SOFT MUTE  
- BASS and TREBLE  
- PARAMETRIC EQ PER CHANNEL  
- BASS MANAGEMENT FOR SUBWOOFER  
TQFP44  
ORDERING NUMBER: STA304  
- AUTO MUTE ON ZERO INPUT DETECTION  
4+1 DIRECT DIGITAL AMPLIFICATION  
(DDX™) OUTPUT CHANNELs  
6 CHANNELs PROGRAMMABLE SERIAL  
OUTPUT INTERFACE (by default I2S)  
4 CHANNELs PROGRAMMABLE SERIAL  
INPUT INTERFACE (by default I2S)  
STEREO S/PDIF INPUT INTERFACE  
Intel AC'97 LINK (rev. 2.1) INPUT INTERFACE  
FOR AUDIO AND CONTROL  
EMBEDDED PLL FOR INTERNAL CLOCK  
GENERATION (1024x48 kHz = 49.152 MHz)  
24.576 MHz EXTERNAL INPUT CLOCK OR  
BUILT-IN INDUSTRY STANDARD XTAL  
OSCILLATOR.  
1.0 DESCRIPTION  
The STA304 Digital Audio Processor is a single chip  
device implementing end to end digital solution for  
audio application. In conjunction with STA500 power  
bridge it gives the full digital DSP-to-power high qual-  
ity chain with no need for audio Digital-to-Analog con-  
verters between DSP and power stage.  
ON CHIP AUTOMATIC INPUT SAMPLING  
FREQUENCY DETECTION  
100 dB SNR SAMPLE RATE CONVERTER  
(1KHz SINUSOIDAL INPUT)  
2
I C CONTROL BUS  
LOW POWER 3.3V CMOS TECHNOLOGY  
BLOCK DIAGRAM  
SCL  
10  
SDA  
9
LEFT_B  
LEFT_A  
29  
30  
27  
28  
33  
LRCKI / SYNC  
BICKI / BIT_CL  
3
4
I2C  
RIGHT_B  
RIGHT_A  
SLEFT_A  
I2S  
ROM  
SDI_1 / SDATA_OUT  
SDI_2 / SDATA_IN  
1
2
DDX  
34 SLEFT_B  
23 SRIGHT_A  
24 SRIGHT_B  
RXP  
RXN  
18  
19  
21  
22  
LFE_A  
LFE_B  
S/PDIF  
SRC  
DSP  
43  
43  
LRCKO  
BICKO  
I2S  
SDO_1  
SDO_2  
SDO_3  
43  
43  
43  
RAM  
AC`97  
RESET  
EAPD  
7
PLL  
PowerDown  
35  
14  
XTI  
15  
43  
44  
11  
XTO  
CKOUT  
PWDN  
SA  
January 2002  
1/30  
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.  

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