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ST95P04B1TR PDF预览

ST95P04B1TR

更新时间: 2024-11-24 22:50:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
16页 153K
描述
SERIAL ACCESS SPI BUS 4K 512 x 8 EEPROM

ST95P04B1TR 数据手册

 浏览型号ST95P04B1TR的Datasheet PDF文件第2页浏览型号ST95P04B1TR的Datasheet PDF文件第3页浏览型号ST95P04B1TR的Datasheet PDF文件第4页浏览型号ST95P04B1TR的Datasheet PDF文件第5页浏览型号ST95P04B1TR的Datasheet PDF文件第6页浏览型号ST95P04B1TR的Datasheet PDF文件第7页 
ST95P04  
SERIAL ACCESS SPI BUS 4K (512 x 8) EEPROM  
NOT FOR NEW DESIGN  
1 MILLION ERASE/WRITE CYCLES  
40 YEARS DATA RETENTION  
SINGLE 3V to 5.5V SUPPLY VOLTAGE  
SPI BUS COMPATIBLE SERIAL INTERFACE  
1 MHz CLOCK RATE MAX  
BLOCK WRITE PROTECTION  
STATUS REGISTER  
8
8
16 BYTE PAGE MODE  
WRITE PROTECT  
SELF-TIMED PROGRAMMING CYCLE  
E.S.D.PROTECTION GREATER than 4000V  
1
1
PSDIP8 (B)  
0.25mm Frame  
SO8 (M)  
The ST95P04 will be replaced shortly by the  
updated version ST95040  
Figure 1. Logic Diagram  
DESCRIPTION  
The ST95P04 is a 4K bit Electrically Erasable  
ProgrammableMemory(EEPROM) fabricated with  
SGS-THOMSON’s HighEndurance Single Polysili-  
con CMOS technology. The 4K bit memory is or-  
ganised as 32 pages of 16 bytes. The memory is  
accessed by a simple SPI bus compatible serial  
interface. The bus signals are a serial clock input  
(C), a serial data input (D) and a serial data output  
(Q). The device connected to the bus is selected  
when the chip select input (S) goes low. Commu-  
nications with the chip can be interrupted with a  
hold input (HOLD). The write operation is disabled  
by a write protect input (W).  
V
CC  
D
C
S
Q
ST95P04  
Table 1. Signal Names  
W
C
Serial Clock  
Serial Data Input  
Serial Data Output  
Chip Select  
Write Protect  
Hold  
HOLD  
D
Q
S
V
SS  
AI01063B  
W
HOLD  
VCC  
VSS  
Supply Voltage  
Ground  
June 1996  
1/16  

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