Datasheet > ST8500

ST8500

更新时间： 2023-12-20 18:45:40

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		通信调制解调器
页数	文件大小	规格书
37页	1212K
描述
可编程电源线通信调制解调器片上系统

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ST8500 数据手册

ST8500

Programmable power line communication modem System on Chip

Datasheet - production data

– 1 flexible CRC calculation unit

– 2 USART, 1 UART, 3 SPI, 1 I C

 Cryptographic engine

– AES 128/192/256 engine

– True random number generator

– Pseudo random number generator

QFN56 (7 x 7 x 1 mm)

 Clock management:

– 25 MHz external crystal for system clock

– Integrated 25 MHz oscillator (XOSC) with

Features

frequency synthesizer (FS) and pre-scaler

units to generate internal clock signals

 Programmable power line communication

(PLC) modem System on Chip

 Power management

 Integrated differential PLC analog front-end

– PGA with automatic gain control and ADC

– DAC with transmission pre-driver

– Digital transmission level control

– Zero crossing comparator

– 3.3 V external supply voltage for I/O and

analog

– 2.5 V internal linear regulator for analog

– 1.1 V external supply voltage for digital

– Normal, Slow, Doze and low power modes

– Up to 500 kHz PLC signal bandwidth

 Available in QFN56 package

 High performance, fully programmable real-

time engine dedicated to PLC PHY and real -

time MAC protocol management (400 MHz

max. frequency)

 -40 °C to +105 °C temperature range

Applications

 Smart metering, smart grid and Internet of

– Dedicated code and data SRAM memories

Things applications

 Standard ARM 32-bit Cortex -M4F fully

programmable core for protocol upper layers

and peripherals management

 Suitable for application design compliant with

CENELEC, FCC and ARIB regulations

– 200 MHz maximum frequency

Table 1. Device summary

– 256 kB of embedded SRAM for code and

data

Order code

Package

Packing

– 96 kB of embedded SRAM for data

– 8 kB of embedded shared RAM

– Bootloader ROM memory

ST8500

Tray

QFN56

ST8500TR

Tape and reel

– One Time Programmable (OTP) memory

with dedicated areas available for secure

keys and user information storage

– Serial wire and JTAG interfaces

– 24 multiplexed GPIOs

– 4 general purpose timers

June 2018

DocID031029 Rev 3

1/37

This is information on a product in full production.

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