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ST7MDT20JEMU3 PDF预览

ST7MDT20JEMU3

更新时间: 2024-11-19 22:30:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
154页 1290K
描述
8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE

ST7MDT20JEMU3 数据手册

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ST7232A  
8-BIT MCU WITH 8K FLASH/ROM,  
ADC, 4 TIMERS, SPI, SCI INTERFACE  
Memories  
– 8K dual voltage High Density Flash (HDFlash)  
or ROM with read-out protection capability. In-  
Application Programming and In-Circuit Pro-  
gramming for HDFlash devices  
– 384 bytes RAM  
TQFP32  
7 x 7  
SDIP32  
400mil  
– HDFlash endurance: 100 cycles, data reten-  
tion: 20 years at 55°C  
Clock, Reset And Supply Management  
– Clock sources: crystal/ceramic resonator os-  
2 Communications Interfaces  
cillators and bypass for external clock  
– SPI synchronous serial interface  
– SCI asynchronous serial interface  
– PLL for 2x frequency multiplication  
– Four Power Saving Modes: Halt, Active-Halt,  
Wait and Slow  
1 Analog peripheral (low current coupling)  
Interrupt Management  
– 10-bit ADC with up to 12 robust input ports  
Instruction Set  
– Nested interrupt controller  
– 14 interrupt vectors plus TRAP and RESET  
– 6 external interrupt lines (on 4 vectors)  
Up to 32 I/O Ports  
– 8-bit Data Manipulation  
– 63 Basic Instructions  
– 17 main Addressing Modes  
– 8 x 8 Unsigned Multiply Instruction  
– 24 multifunctional bidirectional I/O lines  
– 17 alternate function lines  
– 10 high sink outputs  
4Timers  
Development Tools  
– Main Clock Controller with: Real time base,  
– Full hardware/software development package  
– In-Circuit Testing capability  
Beep and Clock-out capabilities  
– Configurable watchdog timer  
– two 16-bit Timers with: 2 input captures, 2 out-  
putcompares, PWM and pulse generator  
modes  
Device Summary  
Features  
Program memory - bytes  
RAM (stack) - bytes  
Operating Voltage  
Temp. Range  
ST72F32AK2  
FLASH 8K  
ST7232AK1  
ROM 4K  
ST7232AK2  
ROM 8K  
384 (256)  
3.8V to 5.5V  
up to -40°C to +85°C  
TQFP32 7x7 , SDIP32 400mils  
Package  
Rev. 1  
1/154  
April 2005  
1

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