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ST7MC2R7T6 PDF预览

ST7MC2R7T6

更新时间: 2024-11-19 22:12:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存微控制器和处理器外围集成电路电动机控制电机时钟
页数 文件大小 规格书
294页 4989K
描述
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI

ST7MC2R7T6 技术参数

生命周期:Active零件包装代码:QFP
包装说明:QFP,针数:64
Reach Compliance Code:compliant风险等级:5.71
Is Samacsys:N具有ADC:YES
地址总线宽度:位大小:8
最大时钟频率:16 MHzDMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-XQFP-G64
JESD-609代码:e4长度:10 mm
I/O 线路数量:38端子数量:64
PWM 通道:YES封装主体材料:UNSPECIFIED
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK认证状态:Not Qualified
速度:16 MHz最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

ST7MC2R7T6 数据手册

 浏览型号ST7MC2R7T6的Datasheet PDF文件第2页浏览型号ST7MC2R7T6的Datasheet PDF文件第3页浏览型号ST7MC2R7T6的Datasheet PDF文件第4页浏览型号ST7MC2R7T6的Datasheet PDF文件第5页浏览型号ST7MC2R7T6的Datasheet PDF文件第6页浏览型号ST7MC2R7T6的Datasheet PDF文件第7页 
ST7MC1/ST7MC2  
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,  
BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI  
PRODUCT PREVIEW  
Memories  
– 8K to 60K dual voltage FLASH Program mem-  
ory or ROM with read-out protection capabili-  
ty. In-Application Programming and In-Circuit  
Programming.  
– 384 to 1.5K RAM  
– HDFlash endurance: 100 cycles, data reten-  
tion: 20 years  
TQFP64  
14 x 14  
TQFP44  
10 x 10  
TQFP80  
14 x 14  
Clock, Reset And Supply Management  
– Enhanced reset system  
TQFP32  
7 x 7  
– Enhanced low voltage supervisor (LVD) for  
main supply and auxiliary voltage detector  
(AVD) with interrupt capability  
– Clock sources: crystal/ceramic resonator os-  
cillators and by-pass for external clock, clock  
security system.  
– Four power saving modes: Halt, Active-Halt,  
Wait and Slow  
Interrupt Management  
– Nested interrupt controller  
– 14 interrupt vectors plus TRAP and RESET  
– MCES top level interrupt pin  
– 16 external interrupt lines (on 3 vectors)  
Up to 60 I/O Ports  
– up to 60 multifunctional bidirectional I/O lines  
– up to 41 alternate function lines  
– up to 11 high sink outputs  
SDIP56  
SDIP32  
2 Communication Interfaces  
– SPI synchronous serial interface  
LINSCIasynchronous serial interface  
Brushless Motor Control Peripheral  
– 6 high sink PWM output channels for sine-  
wave or trapezoidal inverter control  
– Motor safety including asynchronous emer-  
gency stop and write-once registers  
– 4 analog inputs for rotor position detection  
(sensorless/hall/tacho/encoder)  
– Permanent magnet motor coprocessor includ-  
ing multiplier, programmable filters, blanking  
windows and event counters  
– Operational amplifier and comparator for cur-  
rent/voltage mode regulation and limitation  
Analog peripheral  
5 Timers  
– 10-bit ADC with 16 input pins  
– Main Clock Controller with: Real time base,  
Beep and Clock-out capabilities  
– Configurable window watchdog timer  
In-circuit Debug  
Instruction Set  
– 8-bit Data Manipulation  
– Two 16-bit timers with: 2 input captures, 2 out-  
put compares, external clock input, PWM and  
pulse generator modes  
– 8-bit PWM Auto-Reload timer with: 2 input  
captures, 4 PWM outputs, output compare  
and time base interrupt, external clock with  
event detector  
– 63 Basic Instructions  
– 17 main Addressing Modes  
– 8 x 8 Unsigned Multiply Instruction  
– True Bit Manipulation  
Development Tools  
– Full hardware/software development package  
Device Summary  
Features  
ST7MC1  
8K  
ST7MC2  
Program memory - bytes  
RAM (stack) - bytes  
16K  
24K  
1024 (256)  
32K  
48K  
60K  
384 (256)  
768 (256)  
1024 (256)  
1536 (256)  
1536 (256)  
Watchdog, 16-bit Timer A, LINSCI  
, 10-bit ADC, MTC, 8-bit PWM ART, ICD  
SPI, 16-bit Timer B  
Peripherals  
-
Operating  
Supply vs. Frequency  
4.5 to 5.5V with f  
8MHz  
CPU  
-40°C to +85°C  
/ -40°C to +125°C  
Temperature Range  
Package  
-40°C to +85 °C  
TQFP64  
SDIP32/TQFP32  
TQFP44  
SDIP56/TQFP64  
TQFP80  
Rev. 2.1  
April 2004  
1/294  
This is preliminary information on a new product now in development. Details are subject to change without notice.  
1

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