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ST72171K2 PDF预览

ST72171K2

更新时间: 2024-11-22 22:21:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
4页 114K
描述
REAL-TIME DEVELOPMENT TOOLS FOR THE ST7 MCU FAMILY

ST72171K2 数据手册

 浏览型号ST72171K2的Datasheet PDF文件第2页浏览型号ST72171K2的Datasheet PDF文件第3页浏览型号ST72171K2的Datasheet PDF文件第4页 
ST7MDTx-EMU2B  
REAL-TIME DEVELOPMENT TOOLS  
FOR THE ST7 MCU FAMILY  
FEATURES  
A common Hardware Development System  
mainframe supports the entire ST7 family of  
MCUs, in conjunction with the appropriate  
ST7xxx-DBE Active Probe.  
User defined events may trigger a breakpoint or  
simply define data capture parameters, in  
accordance with user preferences.  
Simple connection of the emulator system to the  
Host PC via parallel port.  
Emulation system may be driven by a Windows-  
based GNU debugger software or DOS  
software running on host PC, allowing full  
control and monitoring of hardware resources.  
Multiple windows allow concurrent real-time  
display of source code, MCU resources, internal  
registers, trace data, etc.  
Log files allow storage and subsequent  
redisplay of any displayed screen for  
subsequent analysis.  
Command files can be used to execute a set of  
debugger commands in batch mode.  
Editable configuration files ensure tailoring of  
working environment to user preferences.  
Special Function Register window - symbolic  
display of SFR  
Real-time source level emulation allows viewing  
and breakpoint setting on high level source  
code rather than on disassembled target code  
for optimum user friendliness.  
64 KBytes of user modifiable and configurable  
emulation RAM, allows memory mapping of all  
ST7 family devices as well as modelling  
hypothetical memory configurations.  
Unlimited breakpoints may be set for any op-  
code fetch or any address access, and  
conditions may be defined for the generation of  
2 external synchronization signals.  
1K by 32-bit wide trace memory allows complex  
and sequential events to be defined on any  
combination of address and data, as well as 3  
internal and 5 external logic signals.  
.
February 2000  
1/4  
123  

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