Datasheet > ST2341S23RG_V2

ST2341S23RG_V2

更新时间： 2024-11-05 12:24:19

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描述
P Channel Enhancement Mode MOSFET

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ST2341S23RG_V2 数据手册

ST2341S23RG

P Channel Enhancement Mode MOSFET

-5.3A

DESCRIPTION

ST2341S23RG is the P-Channel logic enhancement mode power field effect transistor

which is produced using high cell density, DMOS trench technology. This high density

process is especially tailored to minimize on-state resistance. These devices are

particularly suited for low voltage application such as cellular phone and notebook

computer power management, other battery powered circuits, and low in-line power

loss are required. The product is in a very small outline surface mount package.

FEATURE

PIN CONFIGURATION

SOT-23-3L

ꢀ

-20V/-3.3A, R_DS(ON)= 30m-ohm (Typ.)

@VGS = -4.5V

-20V/-2.8A, R_DS(ON)= 40m-ohm

@VGS = -2.5V

-20V/-2.3A, R_DS(ON)= 53m-ohm

@VGS = -1.8V

Super high density cell design for

extremely low R_DS(ON)

Exceptional on-resistance and maximum

DC current capability

SOT-23-3L package design

1.Gate 2.Source 3.Drain

PART MARKING

SOT-23-3L

41YA

Y: Year Code A: Process Code

STANSON TECHNOLOGY

120 Bentley Square, Mountain View, Ca 94040 USA

www.stansontech.com

ST2341SRG3RG 2006. Rev.1

12 3 4 5 6

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