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SSTV16859MTD PDF预览

SSTV16859MTD

更新时间: 2024-01-06 19:47:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路电视光电二极管
页数 文件大小 规格书
8页 171K
描述
Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

SSTV16859MTD 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP64,.32,20
针数:64Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.2
系列:SSTVJESD-30 代码:R-PDSO-G64
JESD-609代码:e3长度:17 mm
逻辑集成电路类型:D FLIP-FLOP湿度敏感等级:2
位数:13功能数量:1
端子数量:64最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP64,.32,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5 V传播延迟(tpd):2.8 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Other Logic ICs最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.1 mm
最小 fmax:200 MHzBase Number Matches:1

SSTV16859MTD 数据手册

 浏览型号SSTV16859MTD的Datasheet PDF文件第2页浏览型号SSTV16859MTD的Datasheet PDF文件第3页浏览型号SSTV16859MTD的Datasheet PDF文件第4页浏览型号SSTV16859MTD的Datasheet PDF文件第5页浏览型号SSTV16859MTD的Datasheet PDF文件第6页浏览型号SSTV16859MTD的Datasheet PDF文件第7页 
March 2001  
Revised July 2002  
SSTV16859  
Dual Output 13-Bit Register with  
SSTL-2 Compatible I/O and Reset  
General Description  
Features  
I Compliant with DDR-I registered module specifications  
The SSTV16859 is a dual output 13-bit register designed  
for use with 184 and 232 pin DDR-1 memory modules. The  
device has a differential input clock, SSTL-2 compatible  
data inputs and a LVCMOS compatible RESET input. The  
device has been designed to meet the JEDEC DDR mod-  
ule register specifications.  
I Operates at 2.5V 0.2V VDD  
I SSTL-2 compatible input structure  
I SSTL-2 compliant output structure  
I Differential SSTL-2 compatible clock inputs  
I Low power mode when device is reset  
I Industry standard 64 pin TSSOP package  
The device has been fabricated on an advanced sub-  
micron CMOS process and is designed to operate at power  
supplies of less than 3.6V’s.  
I Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
Ordering Code:  
Order Number Package Number  
Package Description  
SSTV16859G  
BGA96A  
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
(Note 1)(Note 2)  
SSTV16859MTD  
(Note 2)  
MTD64  
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 1: Ordering code Gindicates Trays.  
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
© 2002 Fairchild Semiconductor Corporation  
DS500414  
www.fairchildsemi.com  

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