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SSTV16859GX PDF预览

SSTV16859GX

更新时间: 2024-11-15 23:34:31
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页数 文件大小 规格书
8页 153K
描述
Memory Driver

SSTV16859GX 数据手册

 浏览型号SSTV16859GX的Datasheet PDF文件第2页浏览型号SSTV16859GX的Datasheet PDF文件第3页浏览型号SSTV16859GX的Datasheet PDF文件第4页浏览型号SSTV16859GX的Datasheet PDF文件第5页浏览型号SSTV16859GX的Datasheet PDF文件第6页浏览型号SSTV16859GX的Datasheet PDF文件第7页 
March 2001  
Revised September 2001  
SSTV16859  
Dual Output 13-Bit Register with  
SSTL-2 Compatible I/O and Reset  
General Description  
Features  
Compliant with DDR-I registered module specifications  
The SSTV16859 is a dual output 13-bit register designed  
for use with 184 and 232 pin DDR-1 memory modules. The  
device has a differential input clock, SSTL-2 compatible  
data inputs and a LVCMOS compatible RESET input. The  
device has been designed to meet the JEDEC DDR mod-  
ule register specifications.  
Operates at 2.5V ± 0.2V VDD  
SSTL-2 compatible input structure  
SSTL-2 compliant output structure  
Differential SSTL-2 compatible clock inputs  
Low power mode when device is reset  
Industry standard 64 pin TSSOP package  
The device has been fabricated on an advanced sub-  
micron CMOS process and is designed to operate at power  
supplies of less than 3.6V’s.  
Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
Ordering Code:  
Order Number Package Number  
Package Description  
SSTV16859GX  
(Note 1)  
BGA96A  
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[TAPE and REEL]  
SSTV16859MTD  
(Note 2)  
MTD64  
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 1: BGA package available in Tape and Reel only.  
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
© 2001 Fairchild Semiconductor Corporation  
DS500414  
www.fairchildsemi.com  

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