SSTV16857CGT PDF预览

SSTV16857CGT

更新时间: 2025-07-20 19:15:03
品牌 Logo 应用领域
瑞萨 - RENESAS 双倍数据速率
页数 文件大小 规格书
10页 398K
描述
带有SSTL_2兼容DDRI/O的寄存缓冲器IC48-TSSOP

SSTV16857CGT 数据手册

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ICSSSTV16857C  
DDR 14-Bit Registered Buffer  
Recommended Applications:  
Pin Configuration  
DDR Memory Modules  
Provides complete DDR DIMM logic solution with  
ICS93V857 or ICS95V857  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Q1  
Q2  
GND  
VDDQ  
Q3  
Q4  
Q5  
GND  
VDDQ  
Q6  
D1  
D2  
GND  
VDD  
D3  
D4  
D5  
D6  
D7  
CLK#  
CLK  
VDD  
GND  
VREF  
RESET#  
D8  
SSTL_2 compatible data registers  
Product Features:  
Differential clock signal  
Meets SSTL_2 signal data  
Supports SSTL_2 class I & II specifications  
Low-voltage operation  
- VDD = 2.3V to 2.7V  
48 pin TSSOP package  
Q7  
VDDQ  
GND  
Q8  
Q9  
VDDQ  
GND  
Q10  
Q11  
Q12  
VDDQ  
GND  
Q13  
Q14  
D9  
D10  
D11  
D12  
VDD  
GND  
D13  
D14  
Truth Table1  
Inputs  
CLK CLK#  
X or X or  
Q Outputs  
Q
RESET#  
D
X or  
L
L
Floating Floating Floating  
48-Pin TSSOP & TVSOP  
H
H
H
L
H
L
6.10 mm. Body, 0.50 mm. pitch = TSSOP  
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)  
H
L or H  
L or H  
X
Q0(2)  
Notes:  
1.  
H = High Signal Level  
L = Low Signal Level  
= Transition LOW-to-HIGH  
= Transition HIGH -to LOW  
X = Irrelevant  
Block Diagram  
2.  
Output level before the indicated  
steady state input conditions were  
established.  
38  
39  
CLK  
CLK#  
34  
RESET#  
R
1
Q1  
CLK  
48  
35  
D1  
VREF  
D1  
To 13 Other Channels  
IDT™ / ICS™ DDR 14-Bit Registered Buffer  
ICSSSTV16857C  

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