Datasheet > SSTE32882KB1

SSTE32882KB1

更新时间： 2024-11-19 14:56:19

品牌	Logo	应用领域
瑞萨 - RENESAS		双倍数据速率
页数	文件大小	规格书
76页	1545K
描述
LOW POWER DDR3 Register + PLL

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SSTE32882KB1 数据手册

DATASHEET

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY

TEST AND QUAD CHIP SELECT

SSTE32882KB1

DRAS, DCAS, and DWE), and indicates whether a parity error

has occurred on the open-drain ERROUT pin (active low). The

convention is even parity; i.e., valid parity is defined as an even

number of ones across the DIMM-independent data inputs

combined with the parity input bit. To calculate parity, all

DIMM-independent D-inputs must be tied to a known logic state.

Description

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock

driver with parity is designed for 1.25V, 1.35V and 1.5V VDD

operation.

All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the

reset (RESET) and MIRROR inputs which are LVCMOS. All

outputs are 1.25V,1.35V and 1.5V CMOS edge-controlled drivers

optimized to drive single terminated 25 to 50 traces in DDR3

RDIMM applications, except the open-drain error (ERROUT)

output. The clock outputs (Yn and Yn) and control net outputs

QnCKEn, QnCSn and QnODTn are designed with a different

strength and skew to compensate for different loading and

equalize signal travel speed.

The DIMM-dependent signals (DCKEn, DODTn, and DCSn) are

not included in the parity check computation.

To ensure defined outputs from the register before a stable clock

has been supplied, RESET must be held in the low state during

power-up.

The SSTE32882KB1 is available in a 176-ball BGA with

0.65mm ball pitch in a 11 x 20 grid. The device pinout supports

outputs on the outer two left and right columns to support easy

DIMM signal routing. Corresponding inputs are placed in a-way

that two devices can be placed back-to-back for four Rank

modules while the data inputs share the same vias. Each input and

output is located close to an associated no ball position or on the

outer two rows to allow low cost via technology combined with

the small 0.65mm ball pitch.

The SSTE32882KB1 has two basic modes of operation

associated with the Quad Chip Select Enable (QCSEN) input.

When the QCSEN input pin is open (or pulled high), the

component has two chip select inputs, DCS0 and DCS1, and two

copies of each chip select output, QACS0, QACS1, QBCS0 and

QBCS1. This is the "QuadCS disabled" mode. When the

QCSEN input pin is pulled low, the component has four chip

select inputs DCS[3:0], and four chip select outputs, QCS[3:0].

This is the "QuadCS enabled" mode. Through the remainder of

this specification, DCS[n:0] will indicate all of the chip select

inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS

enabled. QxCS[n:0] will indicate all of the chip select outputs.

The SSTE32882KB1 includes a high-performance, low-jitter,

low-skew buffer that distributes a differential clock input (CK

and CK) to four differential pairs of clock outputs (Yn and Yn),

and to one differential pair of feedback clock outputs (FBOUT

and FBOUT). The clock outputs are controlled by the input

clocks (CK and CK), the feedback clocks (FBIN and FBIN), and

the analog power inputs (AVDD and AVSS). When AVDD is

grounded, the PLL is turned off and bypassed for test purposes.

The SSTE32882KB1 operates from a differential clock (CK and

CK). Data are registered at the crossing of CK going high, and

CK going low. The data is either driven to the corresponding

device outputs if exactly one of the DCS[n:0] input signals is

driven low.

Based on the control register settings, the device can change its

output characterisitics to match different DIMM net topologies.

The timing can be changed to compensate for different flight time

of signals within the target application. By disabling unused

outputs the power consumption is reduced.

The SSTE32882KB1 accepts a parity bit from the memory

controller on the parity (PAR_IN) input, compares it with the data

received on the DIMM-independent data inputs (DAn, DBAn,

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

SSTE32882KB1

7326/3

12 3 4 5 6 7...76

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