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SST89E54RD2A-40-I-TQJE PDF预览

SST89E54RD2A-40-I-TQJE

更新时间： 2024-09-24 14:44:59
品牌 Logo 应用领域
美国微芯 - MICROCHIP 时钟外围集成电路
页数 文件大小 规格书
84页 1755K
描述
8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP44, ROHS COMPLIANT, MS-026ACB, TQFP-44

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SST89E54RD2A-40-I-TQJE 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：ROHS COMPLIANT, MS-026ACB, TQFP-44针数：44
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.24
Is Samacsys：N具有ADC：NO
地址总线宽度：16位大小：8
最大时钟频率：40 MHzDAC 通道：NO
DMA 通道：NO外部数据总线宽度：8
JESD-30 代码：S-PQFP-G44JESD-609代码：e3
长度：10 mmI/O 线路数量：36
端子数量：44最高工作温度：85 °C
最低工作温度：-40 °CPWM 通道：YES
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
ROM可编程性：FLASH座面最大高度：1.2 mm
速度：40 MHz最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：10 mmuPs/uCs/外围集成电路类型：MICROCONTROLLER
Base Number Matches：1

SST89E54RD2A-40-I-TQJE 数据手册

 浏览型号SST89E54RD2A-40-I-TQJE的Datasheet PDF文件第2页浏览型号SST89E54RD2A-40-I-TQJE的Datasheet PDF文件第3页浏览型号SST89E54RD2A-40-I-TQJE的Datasheet PDF文件第4页浏览型号SST89E54RD2A-40-I-TQJE的Datasheet PDF文件第5页浏览型号SST89E54RD2A-40-I-TQJE的Datasheet PDF文件第6页浏览型号SST89E54RD2A-40-I-TQJE的Datasheet PDF文件第7页 
FlashFlex MCU  
SST89E54RD2A/RDA / SST89E58RD2A/RDA  
SST89V54RD2A/RDA / SST89V58RD2A/RDA  
Data Sheet  
FEATURES:  
•
8-bit 8051-Compatible Microcontroller (MCU)  
with Embedded SuperFlash Memory  
•
Ten Interrupt Sources at 4 Priority Levels  
– Four External Interrupt Inputs  
– Fully Software Compatible  
– Development Toolset Compatible  
– Pin-For-Pin Package Compatible  
SST89E5xRD2A Operation  
– 0 to 40 MHz at 5V  
SST89V5xRD2A Operation  
– 0 to 33 MHz at 3V  
•
•
•
Programmable Watchdog Timer (WDT)  
Programmable Counter Array (PCA)  
Four 8-bit I/O Ports (32 I/O Pins) and  
One 4-bit Port  
Second DPTR register  
Low EMI Mode (Inhibit ALE)  
SPI Serial Interface  
Standard 12 Clocks per cycle, the device has an  
option to double the speed to 6 clocks per cycle.  
TTL- and CMOS-Compatible Logic Levels  
Brown-out Detection  
Low Power Modes  
– Power-down Mode with External Interrupt Wake-up  
– Idle Mode  
Temperature Ranges:  
•
•
•
•
•
•
•
•
1 KByte Internal RAM  
Dual Block SuperFlash EEPROM  
– 16/32 KByte primary block +  
•
•
•
8 KByte secondary block  
(128-Byte sector size for both blocks)  
– Individual Block Security Lock with SoftLock  
– Concurrent Operation during  
In-Application Programming (IAP)  
– Memory Overlay for Interrupt Support during IAP  
•
•
•
Support External Address Range up to 64  
KByte of Program and Data Memory  
Three High-Current Drive Ports (16 mA each)  
Three 16-bit Timers/Counters  
– Commercial (0°C to +70°C)  
– Industrial (-40°C to +85°C)  
Packages Available  
– 40-contact WQFN (Port 4 feature not available)  
– 44-lead PLCC  
•
•
•
Full-Duplex, Enhanced UART  
– 40-pin PDIP (Port 4 feature not available)  
– 44-lead TQFP  
– Framing Error Detection  
– Automatic Address Recognition  
•
All non-Pb (lead-free) devices are RoHS compliant  
PRODUCT DESCRIPTION  
The SST89E5xRD2A/RDA and SST89V5xRD2A/RDA are  
members of the FlashFlex family of 8-bit microcontroller  
products designed and manufactured with SST patented  
and proprietary SuperFlash CMOS semiconductor pro-  
cess technology. The split-gate cell design and thick-oxide  
tunneling injector offer significant cost and reliability bene-  
fits for SST customers. The devices use the 8051 instruc-  
tion set and are pin-for-pin compatible with standard 8051  
microcontroller devices.  
In addition to the 24/40 KByte of EEPROM program mem-  
ory on-chip and 1024 x8 bits of on-chip RAM, the devices  
can address up to 64 KByte of external program memory  
and up to 64 KByte of external RAM.  
The flash memory blocks can be programmed via a stan-  
dard 87C5x OTP EPROM programmer fitted with a special  
adapter and the firmware for SST devices. During power-  
on reset, the devices can be configured as either a slave to  
an external host for source code storage or a master to an  
external host for an in-application programming (IAP) oper-  
ation. The devices are designed to be programmed in-sys-  
tem and in-application on the printed circuit board for  
maximum flexibility. The devices are pre-programmed with  
an example of the bootstrap loader in the memory, demon-  
strating the initial user program code loading or subsequent  
user code updating via the IAP operation. The sample  
bootstrap loader is available for the user’s reference and  
convenience only; SST does not guarantee its functionality  
or usefulness. Chip-Erase or Block-Erase operations will  
erase the pre-programmed sample code.  
The devices come with 24/40 KByte of on-chip flash  
EEPROM program memory which is partitioned into 2  
independent program memory blocks. The primary Block 0  
occupies 16/32 KByte of internal program memory space  
and the secondary Block 1 occupies 8 KByte of internal  
program memory space.  
The 8-KByte secondary block can be mapped to the lowest  
location of the 16/32 KByte address space; it can also be  
hidden from the program counter and used as an indepen-  
dent EEPROM-like data memory.  
©2007 Silicon Storage Technology, Inc.  
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.  
These specifications are subject to change without notice.  
S71339-01-000  
1
1/07  
1234567...84

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