Datasheet > SST5912C_SOIC

SST5912C_SOIC

更新时间： 2024-12-01 12:20:19

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描述
MONOLITHIC DUAL N-CHANNEL JFET

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SST5912C_SOIC 数据手册

SST5912C

MONOLITHIC DUAL

N-CHANNEL JFET

Linear Systems replaces discontinued Siliconix / National SST5912C

FEATURES

The SST5912C are monolithic dual JFETs. The

Improved Direct Replacement for SILICONIX & NATIONAL SST5912C

monolithic dual chip design reduces parasitics and

gives better performance at very high frequencies while

ensuring extremely tight matching. These devices are

an excellent choice for use as wideband differential

amplifiers in demanding test and measurement

applications. The SST5912C is a direct replacement for

discontinued Siliconix and National SST5912C.

LOW NOISE (10KHz)

e_n~ 4nV/√Hz

g_fs≥ 4000µS

HIGH TRANSCONDUCTANCE (100MHz)

ABSOLUTE MAXIMUM RATINGS ¹

@ 25°C (unless otherwise noted)

Maximum Temperatures

Storage Temperature

Operating Junction Temperature

Maximum Power Dissipation

Continuous Power Dissipation (Total)

Maximum Currents

‐65°C to +150°C

‐55°C to +135°C

The 8 Pin SOIC provides ease of manufacturing, and

the symmetrical pinout prevents improper orientation.

(See Packaging Information).

500mW

SST5912C Applications:

Gate Current

50mA

Wideband Differential Amps

High-Speed,Temp-Compensated Single-

Ended Input Amps

Maximum Voltages

Gate to Drain

Gate to Source

‐25V

High-Speed Comparators

Impedance Converters and vibrations

detectors.

MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated)

SYMBOL

|V_GS1– V_GS2

CHARACTERISTIC

Differential Gate to Source Cutoff Voltage

MIN

‐‐

TYP

‐‐

MAX

UNITS

CONDITIONS

V_DG= 10V, I_D= 5mA

∆|V_GS1– V_GS2| / ∆T

Differential Gate to Source Cutoff

Voltage Change with Temperature

Gate to Source Saturation Current Ratio

‐‐

µV/°C

V_DG= 10V, I_D= 5mA

T_A= ‐55°C to +125°C

V_DS= 10V, V_GS= 0V

I_DSS1/ I_DSS2

0.95

‐‐

|I_G1– I_G2

Differential Gate Current

V_DG= 10V, I_D= 5mA

T_A= +125°C

V_DS= 10V, I_D= 5mA, f = 1kHz

g_fs1/ g_fs2

Forward Transconductance Ratio²

0.95

Click To Buy

CMRR

Common Mode Rejection Ratio

‐‐

V_DG= 5V to 10V, I_D= 5mA

ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)

SYMBOL

BV_GSS

V_GS(off)

V_GS(F)

V_GS

CHARACTERISTICS

Gate to Source Breakdown Voltage

Gate to Source Cutoff Voltage

Gate to Source Forward Voltage

Gate to Source Voltage

MIN.

‐25

‐1

‐‐

‐0.3

TYP.

‐‐

0.7

‐‐

MAX.

UNITS

CONDITIONS

I_G= ‐1µA, V_DS= 0V

V_DS= 10V, I_D= 1nA

I_G= 1mA, V_DS= 0V

V_DG= 10V, I_G= 5mA

V_DS= 10V, V_GS= 0V

V_GS= ‐15V, V_DS= 0V

V_DG= 10V, I_D= 5mA

‐5

‐‐

‐4

I_DSS

I_GSS

Gate to Source Saturation Current³

‐‐

‐50

Gate Leakage Current³

Gate Operating Current

‐‐

‐1

I_G

g_fs

Forward Transconductance

Output Conductance

4000

‐‐

10000

100

150

1.2

µS

V_DG= 10V, I_D= 5mA

g_os

C_ISS

C_RSS

e_n

Input Capacitance

Reverse Transfer Capacitance

Noise Figure

V_DG= 10V, I_D= 5mA, f = 1MHz

V_DG= 10V, I_D= 5mA, f = 10kHz, R_G= 100KΩ

V_DG= 10V, I_D= 5mA, f = 100Hz

Equivalent Input Noise Voltage

nV/√Hz

‐‐

V_DG= 10V, I_D= 5mA, f = 10kHz

Notes: 1. Absolute Maximum ratings are limiting values above which serviceability may be impaired 2. Pulse Test: PW ≤ 300µs Duty Cycle ≤ 3%

3. Assumes smaller value in numerator

Available Packages:

SST5912C in SOIC

SST5912C available as bare

die

Please contact Micross for full package and die dimensions:

Email: chipcomponents@micross.com

Web: www.micross.com/distribution.aspx

Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or

other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.

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