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SST5911(8SOIC-B) PDF预览

SST5911(8SOIC-B)

更新时间: 2024-12-01 20:49:43
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描述
Transistor

SST5911(8SOIC-B) 数据手册

  
SST5911  
MONOLITHIC DUAL  
N-CHANNEL JFET  
Linear Systems replaces discontinued Siliconix & National SST5911  
FEATURES  
The SST5911 are monolithic dual JFETs. The  
Improved Direct Replacement for SILICONIX & NATIONAL SST5911  
monolithic dual chip design reduces parasitics and  
gives better performance at very high frequencies while  
ensuring extremely tight matching. These devices are  
an excellent choice for use as wideband differential  
amplifiers in demanding test and measurement  
applications. The SST5911 is a direct replacement for  
discontinued Siliconix and National SST5911.  
LOW NOISE (10KHz)  
en~ 4nV/Hz  
gfs 4000µS  
HIGH TRANSCONDUCTANCE (100MHz)  
ABSOLUTE MAXIMUM RATINGS 1  
@ 25°C (unless otherwise noted)  
Maximum Temperatures  
Storage Temperature  
Operating Junction Temperature  
Maximum Power Dissipation  
Continuous Power Dissipation (Total)  
Maximum Currents  
65°C to +150°C  
55°C to +135°C  
The 8 Pin SOIC provides ease of manufacturing, and  
the symmetrical pinout prevents improper orientation.  
(See Packaging Information).  
500mW  
SST5911 Applications:  
Gate Current  
Maximum Voltages  
Gate to Drain  
Gate to Source  
50mA  
ƒ
ƒ
Wideband Differential Amps  
High-Speed,Temp-Compensated Single-  
Ended Input Amps  
25V  
25V  
ƒ
ƒ
High-Speed Comparators  
Impedance Converters and vibrations  
detectors.  
MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated)  
SYMBOL  
|VGS1 – VGS2  
CHARACTERISTIC  
Differential Gate to Source Cutoff Voltage  
MIN  
‐‐  
TYP  
‐‐  
MAX  
10  
UNITS  
mV  
CONDITIONS  
VDG = 10V, ID = 5mA  
|
|VGS1 – VGS2 | / T  
Differential Gate to Source Cutoff  
Voltage Change with Temperature  
Gate to Source Saturation Current Ratio  
‐‐  
‐‐  
20  
µV/°C  
VDG = 10V, ID = 5mA  
TA = 55°C to +125°C  
VDS = 10V, VGS = 0V  
IDSS1 / IDSS2  
0.95  
‐‐  
‐‐  
‐‐  
‐‐  
1
20  
1
%
nA  
%
|IG1 IG2  
|
Differential Gate Current  
VDG = 10V, ID = 5mA  
TA = +125°C  
VDS = 10V, ID = 5mA, f = 1kHz  
gfs1 / gfs2  
Forward Transconductance Ratio2  
0.95  
Click To Buy  
CMRR  
Common Mode Rejection Ratio  
‐‐  
85  
‐‐  
dB  
VDG = 5V to 10V, ID = 5mA  
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)  
SYMBOL  
BVGSS  
VGS(off)  
VGS(F)  
VGS  
CHARACTERISTICS  
Gate to Source Breakdown Voltage  
Gate to Source Cutoff Voltage  
Gate to Source Forward Voltage  
Gate to Source Voltage  
MIN.  
25  
1  
‐‐  
0.3  
7
TYP.  
‐‐  
‐‐  
0.7  
‐‐  
MAX.  
UNITS  
V
CONDITIONS  
IG = 1µA, VDS = 0V  
VDS = 10V, ID = 1nA  
IG = 1mA, VDS = 0V  
VDG = 10V, IG = 5mA  
VDS = 10V, VGS = 0V  
VGS = 15V, VDS = 0V  
VDG = 10V, ID = 5mA  
5  
‐‐  
4  
IDSS  
IGSS  
Gate to Source Saturation Current3  
‐‐  
40  
50  
50  
mA  
Gate Leakage Current3  
Gate Operating Current  
‐‐  
‐‐  
1  
1  
pA  
IG  
gfs  
Forward Transconductance  
Output Conductance  
4000  
4000  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
7
10000  
10000  
100  
150  
5
1.2  
1
20  
µS  
VDG = 10V, ID= 5mA  
gos  
CISS  
CRSS  
NF  
en  
Input Capacitance  
Reverse Transfer Capacitance  
Noise Figure  
pF  
dB  
VDG = 10V, ID = 5mA, f = 1MHz  
VDG = 10V, ID = 5mA, f = 10kHz, RG = 100KΩ  
VDG = 10V, ID = 5mA, f = 100Hz  
Equivalent Input Noise Voltage  
nV/Hz  
‐‐  
4
10  
VDG = 10V, ID = 5mA, f = 10kHz  
Notes: 1. Absolute Maximum ratings are limiting values above which serviceability may be impaired 2. Pulse Test: PW 300µs Duty Cycle 3%  
3. Assumes smaller value in numerator  
Available Packages:  
SST5911 in SOIC  
SST5911 available as bare die  
Please contact Micross for full package and die dimensions:  
Email: chipcomponents@micross.com  
Web: www.micross.com/distribution.aspx  
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or  
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.  

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