1 Mbit (64K x16) Multi-Purpose Flash
SST39LF100 / SST39VF100
SST39LF/VF1003.0 & 2.7V 1 Mb (x16) MPF memories
Data Sheet
FEATURES:
•
•
Organized as 64K x16
•
Fast Erase and Word-Program
Single Voltage Read and Write Operations
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– 3.0-3.6V for SST39LF100
– 2.7-3.6V for SST39VF100
– Chip Rewrite Time: 1 second (typical)
•
•
Superior Reliability
•
•
Automatic Write Timing
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
– Internal VPP Generation
End-of-Write Detection
Low Power Consumption
– Toggle Bit
– Data# Polling
– Active Current: 20 mA (typical)
– Standby Current: 3 µA (typical)
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Sets
Packages Available
•
•
Sector-Erase Capability
– Uniform 2 KWord sectors
Fast Read Access Time
– 40-lead TSOP (10mm x 14mm)
– 48-ball TFBGA (6mm x 8mm)
– 45 ns for SST39LF100
– 70 ns for SST39VF100
•
Latched Address and Data
PRODUCT DESCRIPTION
The SST39LF/VF100 devices are 64K x16 CMOS Multi-
Purpose Flash (MPF) manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
energy consumed during any Erase or Program operation
is less than alternative flash technologies. The SST39LF/
VF100 also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
alternate
approaches.
The
SST39LF100
and
SST39VF100 write (Program or Erase) with a single volt-
age power supply of 3.0-3.6V and 2.7-3.6V, respectively.
Featuring high performance Word-Program, the SST39LF/
VF100 devices provide a typical Word-Program time of 14
µsec. The devices use Toggle Bit or Data# Polling to detect
the completion of the Program or Erase operation. To pro-
tect against inadvertent write, the SST39LF/VF100 have
on-chip hardware and software data protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, the SST39LF/VF100 are offered with a guar-
anteed endurance of 10,000 cycles. Data retention is rated
at greater than 100 years.
To meet surface mount requirements, the SST39LF/VF100
are offered in 40-lead TSOP and 48-ball TFBGA packages.
See Figure 1 for pinout.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39LF/VF100 devices are suited for applications
that require convenient and economical updating of pro-
gram, configuration, or data memory. For all system appli-
cations, the SST39LF/VF100 significantly improve
performance and reliability, while lowering power consump-
tion. The SST39LF/VF100 inherently use less energy dur-
ing Erase and Program than alternative flash technologies.
The total energy consumed is a function of the applied volt-
age, current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
©2001 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
S71129-02-000 6/01
1
363
These specifications are subject to change without notice.
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