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SST112G

更新时间： 2024-11-16 21:11:27
品牌 Logo 应用领域
CALOGIC 瞄准线开关光电二极管晶体管
页数 文件大小 规格书
1页 25K
描述
Small Signal Field-Effect Transistor, 1-Element, N-Channel, Silicon, Junction FET, PLASTIC PACKAGE-3

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中文翻译

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SST112G 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：SMALL OUTLINE, R-PDSO-G3Reach Compliance Code：compliant
HTS代码：8541.21.00.95风险等级：5.67
其他特性：LOW INSERTION LOSS配置：SINGLE
最大漏源导通电阻：50 ΩFET 技术：JUNCTION
JESD-30 代码：R-PDSO-G3元件数量：1
端子数量：3工作模式：DEPLETION MODE
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：N-CHANNEL表面贴装：YES
端子形式：GULL WING端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

SST112G 数据手册

  
N-Channel JFET Switch  
LLC  
J111 - J113 / SST111 – SST113  
FEATURES  
APPLICATIONS  
Low Cost  
Automated Insertion Package  
Low Insertion Loss  
No Offset or Error Voltage Generated By Closed Switch  
Analog Switches  
Choppers  
Commutators  
•
•
•
•
•
•
•
ABSOLUTE MAXIMUM RATINGS  
Purely Resistive  
High Isolation Resistance From Driver  
Fast Switching  
-
(TA = 25oC unless otherwise specified)  
-
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -35V  
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA  
Storage Temperature Range . . . . . . . . . . . . . -55oC to +150oC  
Operating Temperature Range . . . . . . . . . . . -55oC to +135oC  
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300oC  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW  
Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . 3.3mW/oC  
NOTE: Stresses above those listed under "Absolute Maximum  
Ratings" may cause permanent damage to the device. These are  
stress ratings only and functional operation of the device at these or  
any other conditions above those indicated in the operational sections  
of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
•
Short Sample and Hold Aperture Time  
•
PIN CONFIGURATION  
SOT-23  
G
TO-92  
D
ORDERING INFORMATION  
S
Part  
Package  
Temperature Range  
J111-113  
Plastic TO-92  
-55oC to +135oC  
-55oC to +135oC  
PRODUCT MARKING (SOT-23)  
SST111-113 Plastic SOT-23  
G
S
D
For Sorted Chips in Carriers see 2N4391 series.  
SST111  
SST112  
SST113  
111  
112  
113  
5001  
ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified)  
111  
112  
113  
SYMBOL  
PARAMETER  
UNITS  
nA  
TEST CONDITIONS  
MIN TYP MAX MIN TYP MAX MIN TYP MAX  
IGSSR  
VGS(off)  
BVGSS  
IDSS  
Gate Reverse Current (Note 1)  
Gate Source Cutoff Voltage  
-1  
-1  
-5  
-1  
-3  
VDS = 0V, VGS = -15V  
VDS = 5V, ID = 1µA  
VDS = 0V, IG = -1µA  
VDS = 15V, VGS = 0V  
VDS = 5V, VGS = -10V  
VDS = 0.1V, VGS = 0V  
VDS = 0,  
-3  
-35  
20  
-10  
-1  
-35  
5
-0.5  
-35  
2
V
Gate Source Breakdown Voltage  
Drain Saturation Current (Note 2)  
Drain Cutoff Current (Note 1)  
Drain Source ON Resistance  
Drain Gate OFF Capacitance  
mA  
nA  
Ω
ID(off)  
1
30  
5
1
50  
5
1
100  
5
rDS(on)  
Cdg(off)  
Csg(off)  
Cdg(on)  
V
GS = -10V  
Source Gate OFF Capacitance  
5
5
5
(Note 3)  
pF  
f = 1MHz  
Drain Gate Plus Source Gate ON  
V
DS = VGS = 0  
(Note 3)  
28  
28  
28  
+ Csg(on) Capacitance  
td(on) Turn On Delay Time  
tr  
7
6
7
6
7
6
Switching Time Test  
Conditions (Note 3)  
Rise Time  
J111  
10V  
J112  
10V  
-7V  
J113  
10V  
-5V  
ns  
td(off)  
Turn Off Delay Time  
20  
20  
20  
VDD  
V
RL  
GS(off)-12V  
tf  
Fall Time  
15  
15  
15  
0.8kΩ 1.6kΩ 3.2kΩ  
NOTES: 1. Approximately doubles for every 10oC increase in TA.  
2. Pulse test duration 300µs; duty cycle ≤3%.  
3. For design reference only, not 100% tested.  
CALOGIC LLC, 237 WHITNEY PLACE, FREMONT, CA 94539. 510-656-2900 PHONE, 510-651-1076 FAX  
DS039 REV A  
1

中文翻译

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