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SSR2N60ATF PDF预览

SSR2N60ATF

更新时间: 2024-11-06 13:14:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管
页数 文件大小 规格书
9页 645K
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SSR2N60ATF 数据手册

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November 2001  
SSR2N60B / SSU2N60B  
600V N-Channel MOSFET  
General Description  
Features  
These N-Channel enhancement mode power field effect  
transistors are produced using Fairchild’s proprietary,  
planar, DMOS technology.  
This advanced technology has been especially tailored to  
minimize on-state resistance, provide superior switching  
performance, and withstand high energy pulse in the  
avalanche and commutation mode. These devices are well  
suited for high efficiency switch mode power supplies.  
1.8A, 600V, R  
= 5.0@V = 10 V  
DS(on) GS  
Low gate charge ( typical 12.5 nC)  
Low Crss ( typical 7.6 pF)  
Fast switching  
100% avalanche tested  
Improved dv/dt capability  
D
!
D
!
G
I-PAK  
SSU Series  
D-PAK  
SSR Series  
G
S
G D S  
!
S
Absolute Maximum Ratings  
T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
SSR2N60B / SSU2N60B  
Units  
V
V
I
Drain-Source Voltage  
600  
1.8  
DSS  
- Continuous (T = 25°C)  
Drain Current  
A
D
C
- Continuous (T = 100°C)  
1.1  
A
C
I
(Note 1)  
Drain Current  
- Pulsed  
6.0  
A
DM  
V
E
I
Gate-Source Voltage  
± 30  
120  
V
GSS  
AS  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
mJ  
A
1.8  
AR  
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
4.4  
mJ  
V/ns  
W
AR  
dv/dt  
5.5  
Power Dissipation (T = 25°C) *  
2.5  
P
A
D
Power Dissipation (T = 25°C)  
44  
W
C
- Derate above 25°C  
Operating and Storage Temperature Range  
0.35  
-55 to +150  
W/°C  
°C  
T , T  
J
stg  
Maximum lead temperature for soldering purposes,  
T
300  
°C  
L
1/8" from case for 5 seconds  
Thermal Characteristics  
Symbol  
Parameter  
Typ  
--  
Max  
2.87  
50  
Units  
°C/W  
°C/W  
°C/W  
R
R
R
Thermal Resistance, Junction-to-Case  
Thermal Resistance, Junction-to-Ambient *  
Thermal Resistance, Junction-to-Ambient  
θJC  
θJA  
θJA  
--  
--  
110  
* When mounted on the minimum pad size recommended (PCB Mount)  
©2001 Fairchild Semiconductor Corporation  
Rev. B, November 2001  

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