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SSM3K15ACT PDF预览

SSM3K15ACT

更新时间: 2024-11-11 11:58:59
品牌 Logo 应用领域
东芝 - TOSHIBA 晶体开关小信号场效应晶体管
页数 文件大小 规格书
5页 216K
描述
Load Switching Applications

SSM3K15ACT 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:CHIP CARRIER, R-XBCC-N3针数:3
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.2外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE AND RESISTOR最小漏源击穿电压:30 V
最大漏极电流 (ID):0.1 A最大漏源导通电阻:6 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-XBCC-N3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:N-CHANNEL
认证状态:Not Qualified表面贴装:YES
端子形式:NO LEAD端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

SSM3K15ACT 数据手册

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SSM3K15ACT  
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type (U-MOS III)  
SSM3K15ACT  
Load Switching Applications  
Unit: mm  
2.5 V drive  
Low ON-resistance: R  
R
= 3.6 (max) (@V  
= 6.0 (max) (@V  
= 4 V)  
= 2.5 V)  
DS(ON)  
GS  
DS(ON)  
GS  
Absolute Maximum Ratings (Ta = 25°C)  
Characteristics  
Drain-Source voltage  
Symbol  
Rating  
Unit  
V
V
30  
± 20  
V
V
DSS  
Gate-Source voltage  
GSS  
DC  
I
100  
D
Drain current  
mA  
Pulse  
I
400  
DP  
Power dissipation  
P (Note 1)  
100  
mW  
°C  
D
Channel temperature  
Storage temperature range  
T
ch  
150  
T
stg  
55 to 150  
°C  
CST3  
Note:  
Using continuously under heavy loads (e.g. the application of  
high temperature/current/voltage and the significant change in  
temperature, etc.) may cause this product to decrease in the  
reliability significantly even if the operating conditions (i.e.  
operating temperature/current/voltage, etc.) are within the  
absolute maximum ratings.  
JEDEC  
JEITA  
TOSHIBA  
2-1J1B  
Weight: 0.75 mg (typ.)  
Please design the appropriate reliability upon reviewing the  
Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and  
individual reliability data (i.e. reliability test report and estimated failure rate, etc).  
Note 1: Mounted on FR4 board  
(10 mm × 10 mm × 1.0 mm, Cu Pad: 100 mm )  
2
Marking (Top View)  
Pin Condition (Top View)  
Equivalent Circuit  
Polarity mark  
Polarity mark (on the top)  
3
1
3
DI  
2
1. Gate  
2. Source  
1
2
3. Drain  
*Electrodes: On the bottom  
1
2010-11-29  

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