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SPI-4

更新时间： 2024-11-26 06:13:23

品牌	Logo	应用领域
其他 - ETC		可编程逻辑器件先进先出芯片
页数	文件大小	规格书
3页	106K
描述
Core w/ FIFOs V1.0 For Altera PLDs

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SPI-4 数据手册

Product Brief

SPI-4 Phase 1

odel^

are

Core w/ FIFOs V1.0

For Altera PLDs

June 2001

Standards to Silicon

Features

Benefits

•

OIF-compliant SPI-4 Phase

•

Faster FPGA and ASIC development for

improved time-to-market with FlexBUS-

4 functions

(compatible with AMCC FlexBUS-4)

with FIFOs

•

ATM, Packet Over SONET (POS),

and Direct Data Mapping¹modes

•

Lower development cost through design

reuse

Single- and multi-link operation,

scalable from 1 to 16 links.

Available source code licensing for easy

design integration and migration to gate

arrays or ASICs

Programmable per-port bandwidth

allocation

•

Ample design flexibility using control

signals and generics/parameters

Programmable FIFO size with

programmable almost empty/almost

full thresholds.

Verified functionality and standards

compliance

•

Programmable burst size

Description

Automatic link selection in the

Source block based on Source

FIFO threshold and flow control

information.

The Optical Interworking Forum’s (OIF) SPI-

4 Phase 1 interface allows the

interconnection of Physical Layer devices to

Link Layer devices in 10Gb/s ATM, POS,

and Ethernet applications. Modelware’s

SPI-4 Phase 1 core performs the interface

functions on both sides of the interface as

shown in Figure 1and Figure 2.

•

64-bit data bus width.

Parity generation/checking over

data and control words

•

Altera’s Atlantic Interface on user’s

side.

Spi4

Line Tx

Data

Full synchronous design, exceeds:

Clk = 200 MHz

Spi4Tx

FIFO(s)

PHY

Link

Layer

SPI-4

I/F

Layer

PluriBus

Interface

Fully automatic test bench including

driver/monitor.

Processor

Line Rx

Data

Spi4Rx

FIFO(s)

Easy to use in Mux/Demux and

bridge functions

Control

Status

Standards Compliance

Figure 1: SPI-4 Phase 1 PHY Layer Application

•

OIF SPI-4 Phase 1

•

AMCC FlexBUS-4

¹Direct Data Mapping is a raw data mode

supported in AMCC’s Ganges device.

12 3

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