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SPC58EH84C5 PDF预览

SPC58EH84C5

更新时间: 2024-11-26 02:43:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
7页 300K
描述
A scalable approach for high-end body, networking and security platforms for Automotive

SPC58EH84C5 数据手册

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SPC58EHx, SPC58NHx  
A scalable approach for high-end body, networking and security  
platforms for Automotive  
Data brief  
Comprehensive new generation ASIL-D safety  
concept:  
– ASIL-D of ISO 26262  
– One CPU channel in lockstep  
eTQFP144 (20x20x1 mm)  
FPBGA302 (17x17x1.8 mm)  
eLQFP176 (24x24x1 mm)  
FPBGA386 (19x19x1.8 mm)  
– Logic BIST  
– FCCU for collection and reaction to failure  
notifications  
– Memory BIST  
– Cyclic redundancy check (CRC) unit  
Features  
– Memory Error Management Unit (MEMU)  
for collection and reporting of error events  
in memories  
AEC-Q100 qualified  
High performance e200z4 triple core:  
– 32-bit Power Architecture technology CPU  
– Core frequency as high as 200 MHz  
– Variable Length Encoding (VLE)  
Crossbar switch architecture for concurrent  
access to peripherals, Flash, or RAM from  
multiple bus masters with end-to-end ECC  
Body cross triggering unit (BCTU):  
– Floating Point, End-to-End Error Correction  
– Triggers ADC conversions from any eMIOS  
channel  
10496 KB (10240 KB code Flash + 256 KB  
data Flash) on-chip Flash memory:  
– Triggers ADC conversions from up to 2  
dedicated PIT_RTIs  
– Supports read during program and erase  
operations, and multiple blocks allowing  
EEPROM emulation  
Enhanced modular IO subsystem (eMIOS):  
– up to 96 timed IO channels with 16-bit  
counter resolution  
– Supports read while read between the two  
code Flash partitions  
Enhanced analog-to-digital converter system  
– Hardware support for Flash context  
switching (for FOTA with multi software  
versions)  
with:  
– 4 independent fast 12-bit SAR analog  
converters  
1088 KB on-chip general-purpose SRAM (in  
– One supervisor 12-bit SAR analog  
converter  
addition to 192 KB core local data RAM):  
– 64 KB in CPU_0, 64 KB in CPU_1 and  
64 KB in CPU_2  
– One standby 10-bit SAR analog converter  
– 100 ADC channels  
224 KB HSM dedicated Flash memory (192 KB  
Communication interfaces:  
code + 32 KB data)  
– 24 LINFlexD modules  
Multi-channel direct memory access controller  
– 10 deserial serial peripheral interface  
(DSPI) modules  
(eDMA):  
– One eDMA with 64 channels  
– One eDMA with 16 channels  
– 1 deserial serial peripheral interface  
(DSPI_LP) module available in low power  
mode  
One interrupt controller (INTC)  
July 2020  
DB3758 Rev 2  
1/7  
For further information contact your local STMicroelectronics sales office.  
www.st.com  
 

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