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SPC58EC80E7 PDF预览

SPC58EC80E7

更新时间: 2024-11-26 14:57:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
153页 2761K
描述
用于汽车一般用途应用的32位Power Architecture MCU - Chorus系列

SPC58EC80E7 数据手册

 浏览型号SPC58EC80E7的Datasheet PDF文件第2页浏览型号SPC58EC80E7的Datasheet PDF文件第3页浏览型号SPC58EC80E7的Datasheet PDF文件第4页浏览型号SPC58EC80E7的Datasheet PDF文件第5页浏览型号SPC58EC80E7的Datasheet PDF文件第6页浏览型号SPC58EC80E7的Datasheet PDF文件第7页 
SPC584Cx, SPC58ECx  
SPC58 C Line - 32 bit Power Architecture automotive MCU  
Dual z4 cores 180 MHz, 4 MBytes Flash, HSM, ASIL-B  
Datasheet - production data  
– Memory Error Management Unit (MEMU)  
for collection and reporting of error events  
in memories  
– Cyclic redundancy check (CRC) unit  
eTQFP64 (10 x 10 x 1.0 mm)  
eTQFP100 (14 x 14 x 1.0 mm)  
Crossbar switch architecture for concurrent  
access to peripherals, Flash, or RAM from  
multiple bus masters with end-to-end ECC  
Body cross triggering unit (BCTU)  
eTQFP144 (20 x 20 x 1.0 mm) eLQFP176 (24 x 24 x 1.4 mm)  
– Triggers ADC conversions from any eMIOS  
channel  
– Triggers ADC conversions from up to 2  
dedicated PIT_RTIs  
FPBGA292 (17 x 17 x 1.8 mm)  
Enhanced modular IO subsystem (eMIOS): up  
to 64 timed I/O channels with 16-bit counter  
resolution  
Features  
Enhanced analog-to-digital converter system  
AEC-Q100 qualified  
with:  
High performance e200z420n3 dual core  
– 32-bit Power Architecture technology CPU  
– Core frequency as high as 180 MHz  
– Variable Length Encoding (VLE)  
– 3 independent fast 12-bit SAR analog  
converters  
– 1 supervisor 12-bit SAR analog converter  
– 1 10-bit SAR analog converter with STDBY  
mode support  
4224 KB (4096 KB code flash + 128 KB data  
flash) on-chip flash memory: supports read  
during program and erase operations, and  
multiple blocks allowing EEPROM emulation  
Communication interfaces  
– 18 LINFlexD modules  
– 8 deserial serial peripheral interface (DSPI)  
modules  
176 KB HSM dedicated flash memory (144 KB  
code + 32 KB data)  
– 8 MCAN interfaces with advanced shared  
memory scheme and ISO CAN-FD support  
384 KB on-chip general-purpose SRAM (in  
addition to 128 KB core local data RAM: 64 KB  
included in each CPU)  
– Dual-channel FlexRay controller  
– 1 ethernet controller 10/100 Mbps,  
compliant IEEE 802.3-2008  
Multi-channel direct memory access controller  
(eDMA) with 64 channels  
Low power capabilities  
– Versatile low power modes  
– Ultra low power standby with RTC  
– Smart Wake-up Unit for contact monitoring  
– Fast wakeup schemes  
1 interrupt controller (INTC)  
Comprehensive new generation ASIL-B safety  
concept  
– ASIL-B of ISO 26262  
– FCCU for collection and reaction to failure  
notifications  
Dual phase-locked loops with stable clock  
domain for peripherals and FM modulation  
domain for computational shell  
May 2021  
DS11620 Rev 8  
1/153  
This is information on a product in full production.  
www.st.com  
 

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