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SPC584B70E1EG01Y PDF预览

SPC584B70E1EG01Y

更新时间: 2024-11-26 06:10:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 微控制器
页数 文件大小 规格书
142页 3106K
描述
Microcontroller

SPC584B70E1EG01Y 数据手册

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SPC584Bx  
32-bit Power Architecture microcontroller for automotive ASIL-B  
applications  
Datasheet - production data  
– Memory Error Management Unit (MEMU)  
for collection and reporting of error events  
in memories  
– Cyclic redundancy check (CRC) unit  
eTQFP64 (10 x 10 x 1.0 mm)  
eTQFP100 (14 x 14 x 1.0 mm)  
Enhanced low power support  
– Ultra low power STANDBY  
– Smart Wake-up Unit  
– Fast wake-up and execute from RAM  
Enhanced modular IO subsystem (eMIOS): up  
eTQFP144 (20 x 20 x 1.0 mm)  
eTQFP176 (24 x 24 x 1.4 mm)  
to 64 timed I/O channels with 16-bit counter  
resolution  
Features  
Body cross triggering unit (BCTU)  
AEC-Q100 qualified  
– Triggers ADC conversions from any eMIOS  
channel  
High performance e200z420  
– Triggers ADC conversions from up to 2  
dedicated PIT_RTIs  
– 32-bit Power Architecture technology CPU  
– Core frequency as high as 120 MHz  
– Variable Length Encoding (VLE)  
Enhanced analog-to-digital converter system  
with:  
2112 KB (2048 KB code flash + 64 KB data  
flash) on-chip flash memory: supports read  
during program and erase operations, and  
multiple blocks allowing EEPROM emulation  
– 2 independent fast 12-bit SAR analog  
converters  
– 1 supervisor 12-bit SAR analog converter  
– 1 10-bit SAR analog converter with STDBY  
mode support  
176 KB HSM dedicated flash memory (144 KB  
code + 32 KB data)  
Communication interfaces  
128 KB on-chip general-purpose SRAM (in  
– 1 Ethernet controller 10/100 Mbps,  
compliant IEEE 802.3-2008  
addition to 64 KB core local data RAM  
Crossbar switch architecture for concurrent  
access to peripherals, Flash, or RAM from  
multiple bus masters with end-to-end ECC  
– 8 MCAN interfaces with advanced shared  
memory scheme and ISO CAN-FD support  
– 14 LINFlexD modules  
Multi-channel direct memory access controller  
– 7 Deserial Serial Peripheral Interface  
(DSPI) modules  
(eDMA) with 64 channels  
1 interrupt controller (INTC)  
Dual phase-locked loops with stable clock  
domain for peripherals and FM modulation  
domain for computational shell  
Comprehensive new generation ASIL-B safety  
concept  
– ASIL-B of ISO 26262  
Nexus Development Interface (NDI) per IEEE-  
ISTO 5001-2003 standard, with some support  
for 2010 standard  
– FCCU for collection and reaction to failure  
notifications  
September 2019  
DS11701 Rev 4  
1/142  
This is information on a product in full production.  
www.st.com  
 

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