Datasheet > SPC5676RDK3MVY1

SPC5676RDK3MVY1

更新时间： 2024-10-29 15:18:23

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
111页	2157K
描述
NXP 32-bit MCU, Power Arch core, 6MB Flash, 184MHz, -40/+125degC, Automotive Grade, PBGA 516

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SPC5676RDK3MVY1 数据手册

Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5676R

Rev. 4, 16 Feb 2016

MPC5676R

MPC5676R Microcontroller

Data Sheet

TEPBGA–416

27 mm x 27 mm

TEPBGA–516

27mm x 27mm

On-chip modules available within the family include the

following features:

– Up to 96 eTPU2 channels (32 channels per eTPU2)

– total of 36 KB code RAM

– total of 9 KB parameter RAM

• Two identical dual issue, 32-bit CPU core complexes

(e200z7), each with

• Enhanced modular input output system supporting 32

unified channels (eMIOS) with each channel capable of

single action, double action, pulse width modulation

(PWM) and modulus counter operation

• Two enhanced queued analog-to-digital converter

(eQADC) modules with

– Power Architecture embedded specification compliance

– Instruction set enhancement allowing variable length

encoding (VLE), optional encoding of mixed 16-bit and

32-bit instructions, for code size footprint reduction

– Signal processing extension (SPE) instruction support

for digital signal processing (DSP)

– two separate analog converters per eQADC module

– support for a total of 64 analog input pins, expandable to

176 inputs with off-chip multiplexers

– Single-precision floating point operations (FPU)

– 16 KB I-Cache and 16 KB D-Cache

– Hardware cache coherency between cores

• 16 Hardware semaphores

• 3 channel CRC module

• 6MB on-chip flash

– Supports read during program and erase operations, and

multiple blocks allowing EEPROM emulation

• 384KB on-chip general-purpose SRAM including 48KB of

standby RAM

• Two multi-channel direct memory access controllers

(eDMA)

– one absolute reference ADC channel

– interface to twelve hardware decimation filters

– enhanced ‘Tap’ command to route any conversion to two

separate decimation filters

– Temperature sensor

• Five deserial serial peripheral interface (DSPI) modules

• Three enhanced serial communication interface (eSCI)

modules

• Four controller area network (FlexCAN) modules

• Dual-channel FlexRay controller

• Nexus development interface (NDI) per IEEE-ISTO

5001-2003 standard, with some support for 2010 standard.

• Device and board test support per Joint Test Action Group

(JTAG) (IEEE 1149.1)

• On-chip voltage regulator controller regulates supply

voltage down to 1.2 V for core logic

– 64 channels per eDMA

• Dual core Interrupt controller (INTC)

• Phase-locked loop with FM modulation (FMPLL)

• Crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters

• External Bus Interface (EBI) for calibration and

application development

• Self Test capability

• System integration unit (SIU) with error correction status

module (ECSM)

• Four protected port output pins (PPO)

• Boot assist module (BAM) supports serial bootload via

CAN or SCI

• Three second-generation enhanced time processor units

(eTPU2)

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

12 3 4 5 6 7...111

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