SP8855E
2.8GHz Parallel Load Professional Synthesiser
Advance Information
DS4239
ISSUE 3.0
PIN 1
March 1999
The SP8855E is one of a family of parallel load
synthesisers containing all the elements apart from the loop
amplifier to fabricate a PLL synthesis loop. Other devices in
the series are the SP8852E which is a fully programmable
device requiring two 16 bit words to set the RF and reference
counters, and the SP8854E which has hard wired reference
counter programming and requires a single bit word to pro-
gram the RF divider. The SP8855E replaces the existing
SP8855D.
The SP8855E is intended for applications where a fixed
synthesiserfrequencyisrequiredalthoughitcanalsobeused
where frequency selection is set by switches. In general the
device will be programmed by connecting the programming
pins to either VCC or ground. Additional hard wired inputs can
HC44
be used to control the Fpd and Fref outputs set the control
direction of the loop and select the phase detector gain.
Another input may be used to disable the phase detector
output.
The device is available in both plastic (HP) and ceramic
(HC) J-leaded 44-lead chip carrier. Ambient temperature
ranges available are shown in the ordering information.
OPTIONAL
PIN 1
REFERENCE
Features
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2.8GHz Operating Frequency (IG GRADE)
Single 5V Supply Operation
HP44
High Comparison Frequency 50MHz
High Gain Phase Detector 1mA/rad
Programmable Phase Detector Gain
Zero "Dead Band" Phase Detector
Wide range of RF and Reference Divide Ratios
Programming by Hard Wired Inputs
Low cost plastic package option
Pin
1
2
3
4
5
6
7
8
Description
Pin Description
Control Direction
Input bus bit 10
Input bus bit 9
Input bus bit 8
Input bus bit 7
Input bus bit 6
Input bus bit 5
Input bus bit 4
Input bus bit 3
Input bus bit 2
Input bus bit 1
Input bus bit 0
0V (prescaler)
RF input
RF input
VCC + 5V (prescaler)
VEE 0V
Lock detect output
C-lock detect
Rset
Charge pump output
Charge pump ref.
Fref/Fpd enable
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Fpd*
Fref*
+5V
Ref. osc capacitor
Ref in/XTAL
Reference bit 9
Reference bit 8
Reference bit 7
Reference bit 6
Reference bit 5
Reference bit 4
Reference bit 3
Reference bit 2
Reference bit 1
Reference bit 0
Phase Detect Enable
Phase Detect Gain 1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GPS HI-REL level a screened option
Absolute Maximum Ratings
Supply voltage
Storage temperature
Operating temperature
Prescaler & reference Input Voltage
-0.3V to 6V
-65 °C to +150°C
-55°C to +100°C
2.5V p-p
Data Inputs
VCC +0.3V
Phase Detect Gain
Input bus bit 13
Input bus bit 12
Input bus bit 11
0
VEE -0.3V
Junction temperature
+ 175°C (HC package)
+ 150°C (HP package)
*Fpd and Fref outputs are reversed using the Control Direction
input. The table above is correct when pin 23 is high.
Figure 1 - Pin connections - top view