Datasheet > SP8782MP2Q

SP8782MP2Q

更新时间： 2024-01-06 04:52:06

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
8页	291K
描述
1GHz 16/17, 32/33 Multi-Modulus Divider

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数据手册

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SP8782MP2Q 数据手册

SP8782A & B

1GHz 16/17, 32/33 Multi-Modulus Divider

March 2006

Features

Ordering Information

•

Advanced Resynchronisation techniques to negate

SP8782/B/MP

SP8782/A/DG

8 Pin SOP/SOIC

8 Pin CERDIP

SP8782/B/MPTC 8 Pin SOP/SOIC

SP8782/B/MP2Q 8 Pin SOP/SOIC**

Tubes

Tape & Reel

loop delay effects

•

CMOS compatible output capability

Multi-Modulus division

Available as DESC SMD 5962-9208901MPA

**Pb Free Tin/Silver/Copper

Description

Absolute Maximum Ratings

Supply Voltage

Clock input level

2.5V p-p

+175 C

The SP8782 is a multi-modulus divider which divides by 16/

17 when the Ratio Select input is low and by 32/33 when

theRatio Select input is high. When high, the modulus Control

input selects the lower division ratio (16 or 32) and the higher

ratio (17 or 33) when it is low.

Junction temperature

Storage temperature range:

SP8782A

-55 C to +150 C

-55 C to +125 C

SP8782B

The device uses resynchronisation techniques to reduce the

effects of propagation delays in frequency synthesis.

The SP8782A (ceramic DIL package) is characterised over

the full military temperature range of -55 C to +125 C, the

SP8782B (miniature plastic DIL package) over the industrial

range of -40 C to+85 C.

RATIO

SELECT

V_CC

CLOCK INPUT

16/17

32/33

OUTPUT

CLOCK INPUT

V_EE

MODULUS

CONTROL

INPUT

Figure 1 Functional Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7 8

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SP8785M	DYNEX	获取价格	Prescaler, ECL, CDIP16
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