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SP8782B PDF预览

SP8782B

更新时间: 2024-01-26 08:09:28
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
8页 291K
描述
1GHz 16/17, 32/33 Multi-Modulus Divider

SP8782B 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.5其他特性:SELECTABLE DIVISION RATIO 32/33
系列:8782JESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
逻辑集成电路类型:PRESCALER数据/时钟输入次数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240传播延迟(tpd):3 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4 V
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mm最小 fmax:1000 MHz
Base Number Matches:1

SP8782B 数据手册

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SP8782A & B  
1GHz 16/17, 32/33 Multi-Modulus Divider  
March 2006  
Features  
Ordering Information  
Advanced Resynchronisation techniques to negate  
SP8782/B/MP  
SP8782/A/DG  
8 Pin SOP/SOIC  
8 Pin CERDIP  
SP8782/B/MPTC 8 Pin SOP/SOIC  
SP8782/B/MP2Q 8 Pin SOP/SOIC**  
Tubes  
Tubes  
Tape & Reel  
Tape & Reel  
loop delay effects  
CMOS compatible output capability  
Multi-Modulus division  
Available as DESC SMD 5962-9208901MPA  
**Pb Free Tin/Silver/Copper  
Description  
Absolute Maximum Ratings  
Supply Voltage  
6V  
Clock input level  
2.5V p-p  
+175 C  
The SP8782 is a multi-modulus divider which divides by 16/  
17 when the Ratio Select input is low and by 32/33 when  
theRatio Select input is high. When high, the modulus Control  
input selects the lower division ratio (16 or 32) and the higher  
ratio (17 or 33) when it is low.  
Junction temperature  
Storage temperature range:  
SP8782A  
-55 C to +150 C  
-55 C to +125 C  
SP8782B  
The device uses resynchronisation techniques to reduce the  
effects of propagation delays in frequency synthesis.  
The SP8782A (ceramic DIL package) is characterised over  
the full military temperature range of -55 C to +125 C, the  
SP8782B (miniature plastic DIL package) over the industrial  
range of -40 C to+85 C.  
RATIO  
SELECT  
VCC  
2
1
2
CLOCK INPUT  
7
16/17  
32/33  
OUTPUT  
3
CLOCK INPUT  
4
5
VEE  
MODULUS  
CONTROL  
INPUT  
Figure 1 Functional Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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