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SP8782A PDF预览

SP8782A

更新时间: 2024-11-11 04:03:15
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 逻辑集成电路
页数 文件大小 规格书
8页 291K
描述
1GHz 16/17, 32/33 Multi-Modulus Divider

SP8782A 数据手册

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SP8782A & B  
1GHz 16/17, 32/33 Multi-Modulus Divider  
March 2006  
Features  
Ordering Information  
Advanced Resynchronisation techniques to negate  
SP8782/B/MP  
SP8782/A/DG  
8 Pin SOP/SOIC  
8 Pin CERDIP  
SP8782/B/MPTC 8 Pin SOP/SOIC  
SP8782/B/MP2Q 8 Pin SOP/SOIC**  
Tubes  
Tubes  
Tape & Reel  
Tape & Reel  
loop delay effects  
CMOS compatible output capability  
Multi-Modulus division  
Available as DESC SMD 5962-9208901MPA  
**Pb Free Tin/Silver/Copper  
Description  
Absolute Maximum Ratings  
Supply Voltage  
6V  
Clock input level  
2.5V p-p  
+175 C  
The SP8782 is a multi-modulus divider which divides by 16/  
17 when the Ratio Select input is low and by 32/33 when  
theRatio Select input is high. When high, the modulus Control  
input selects the lower division ratio (16 or 32) and the higher  
ratio (17 or 33) when it is low.  
Junction temperature  
Storage temperature range:  
SP8782A  
-55 C to +150 C  
-55 C to +125 C  
SP8782B  
The device uses resynchronisation techniques to reduce the  
effects of propagation delays in frequency synthesis.  
The SP8782A (ceramic DIL package) is characterised over  
the full military temperature range of -55 C to +125 C, the  
SP8782B (miniature plastic DIL package) over the industrial  
range of -40 C to+85 C.  
RATIO  
SELECT  
VCC  
2
1
2
CLOCK INPUT  
7
16/17  
32/33  
OUTPUT  
3
CLOCK INPUT  
4
5
VEE  
MODULUS  
CONTROL  
INPUT  
Figure 1 Functional Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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