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SP5769A/KG/MP1T PDF预览

SP5769A/KG/MP1T

更新时间: 2024-11-29 15:52:31
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 光电二极管
页数 文件大小 规格书
11页 363K
描述
PLL Frequency Synthesizer, PDSO16, 0.150 INCH, MS-012-AC, SOIC-16

SP5769A/KG/MP1T 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOP, SOP16,.25Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.72
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
功能数量:1端子数量:16
最高工作温度:80 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:PLL or Frequency Synthesis Circuits最大供电电流 (Isup):25 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

SP5769A/KG/MP1T 数据手册

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SP5769  
3GHz I2C Bus Synthesiser  
DS4878  
ISSUE 4.3  
May 2002  
Features  
Ordering Information  
SP5769A/KG/MP1S (Tubes)  
SP5769A/KG/MP1T (Tape and Reel)  
(16 lead SOIC Package)  
SP5769A/KG/QP1S (Tubes)  
SP5769A/KG/QP1T (Tape and Reel)  
(16 lead QSOP Package)  
• Complete 3·0 GHz Single Chip System  
• Optimised for Low Phase Noise, with Comparison  
Frequencies up to 4 MHz  
• No RF Prescaler  
• Selectable Reference Division Ratio  
• Selectable Reference/Comparison Frequency Output  
• Selectable Charge Pump Current with 10:1 Ratio  
• Four Selectable I2C Addresses  
prescaler phase noise degradation over the full RF  
operating range. The comparison frequency is obtained  
either from an on-chip crystal controlled oscillator, or from  
an external source. The oscillator frequency, fREF, or phase  
comparator frequency, fCOMP, can be switched to the REF/  
COMP output providing a reference for a second  
frequency synthesiser. The synthesiser is controlled via  
an 12C bus and is fast mode compliant. It can be hard  
wired to respond to one of four addresses to enable two  
or more synthesisers to be used on a common bus. The  
device contains four switching ports P0 - P3.  
• I2C Fast Mode Compliant with 3·3V and 5V Logic  
Levels  
• Four Switching Ports  
• Functional Replacement for SP5659 (except ADC)  
• Pin Compatible with SP5655  
• Power Consumption 138mW with VCC = 5·5V, all Ports off  
• ESD Protection 2kV min., MIL-STD-883B Method 3015  
Cat.1 (Normal ESD handling procedures should be  
observed)  
Applications  
Absolute Maximum Ratings  
All voltages are referred to VEE = 0V  
• Digital Satellite and Cable Tuning Systems  
• Communications Systems  
Supply voltage, VCC  
RF differential input voltage  
All I/O port DC offsets  
SDA and SCL DC offset  
Storage temperature  
Junction temperature  
MP16 thermal resistance  
Chip to ambient, θJA  
Chip to case, θJC  
-3V to +7V  
2·5Vp-p  
-0·3 to V CC +0·3V  
20·3 to 6V  
-55°C to +125°C  
+150°C  
Description  
The SP5769 is a single chip frequency synthesiser  
designed for tuning systems up to 3GHz. The RF  
preamplifier interfaces direct with the RF programmable  
divider, which is of MN1A construction so giving a step  
size equal to the loop comparison frequency and no  
80°C/W  
20°C/W  
11  
REF/COMP  
2
ENABLE/  
SELECT  
CRYSTAL CAP  
11-BIT  
COUNT  
REFERENCE  
DIVIDER  
13  
RF  
INPUT  
416/17  
3
14  
CRYSTAL  
4-BIT  
COUNT  
1
CHARGE PUMP  
LOCK  
PD  
16  
DRIVE  
PUMP  
f
/2  
CP TEST  
MODE SET  
2 BIT  
4 BIT  
2 BIT  
3 BIT  
15-BIT LATCH  
10  
4
ADDRESS  
SDA  
2
I C BUS  
TRANSCEIVER  
5
SCL  
f /2 SELECT  
PD  
4-BIT LATCH AND  
PORT INTERFACE  
6
7
8
9
P3 P2  
P1 P0  
Figure 1 - SP5769 Block Diagram  

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