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SP5669/KG/MP1S

更新时间： 2024-09-25 19:52:27
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 光电二极管
页数 文件大小 规格书
15页 212K
描述
PLL Frequency Synthesizer, BIPolar, PDSO16, 0.150 INCH, MS-012AC, SOIC-16

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中文翻译

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SP5669/KG/MP1S 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：SOP, SOP16,.25Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.8
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：9.9 mm
功能数量：1端子数量：16
最高工作温度：80 °C最低工作温度：-20 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：5 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电流 (Isup)：85 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BIPOLAR温度等级：COMMERCIAL EXTENDED
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

SP5669/KG/MP1S 数据手册

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SP5669  
2.7GHz I2C Bus Controlled Synthesiser  
Preliminary Information  
DS4852  
ISSUE 2.1  
May 1999  
Features  
Ordering Information  
SP5669/KG/MP1S (Tubes)  
SP5669/KG/MP1T (Tape and reel)  
•
•
•
•
•
•
•
•
•
•
Complete 2.7GHz single chip system  
Compatible with UK DTT offset requirements  
Optimised for low phase noise  
Selectable divide by two prescaler  
Selectable reference division ratio  
Selectable reference/comparison frequency output  
Selectable charge pump current  
The comparison frequency is obtained either from an  
on–chip crystal controlled oscillator, or from an external  
source. The oscillator frequency Fref or the comparison  
frequency Fcomp may be switched to the REF/COMP  
output. This feature is ideally suited to providing the  
referencefrequencyforasecondsynthesisersuchasin  
a double conversion tuner (see Fig. 8).  
Four selectable I2C bus address  
5–level ADC  
Pin compatible with the SP5658 3–wire bus  
controlled synthesiser and SP5659 I2C bus  
synthesiser and SP5659 I2C bus synthesiser  
ESD protection; (Normal ESD handling  
procedures should be observed)  
The synthesiser is controlled via an I 2 C bus, and  
respondstooneoffourprogrammableaddresseswhich  
are selected by applying a specific voltage to the  
‘address’ input. This feature enables two or more  
synthesisers to be used in a system.  
Applications  
•
•
Complete 2.7GHz single chip system  
Optimised for low phase noise  
The device contains four switching ports P0–P3 and a  
5–level ADC. The output of the ADC can be read via the  
I 2 C bus.  
Description  
The SP5669 is a single chip frequency synthesiser  
designed for tuning systems up to 2.7GHz and offers  
step size compatible with DTT offset requirements.  
The device also contains a varactor line disable and  
chargepump disable facility.  
The RF preamplifier drives a divide by two prescaler  
which can be disabled for applications up to 2GHz,  
allowing direct interfacing with the programmable  
divider so enabling a step size equal to the comparison  
frequency. For applications up to 2.7GHz the divide by  
two is enabled, giving a step size of twice the  
comparison frequency.  
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