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SP3203EY PDF预览

SP3203EY

更新时间: 2024-02-18 08:48:51
品牌 Logo 应用领域
西伯斯 - SIPEX /
页数 文件大小 规格书
14页 121K
描述
3V RS-232 Serial Transceiver with Logic Selector

SP3203EY 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.63差分输出:NO
驱动器位数:3输入特性:SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER接口标准:EIA-232-F; TIA-232-F; V.24; V.28; EIA-562; TIA-562
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm湿度敏感等级:1
功能数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
最小输出摆幅:10 V最大输出低电流:0.0016 A
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3/5 V认证状态:Not Qualified
最大接收延迟:接收器位数:2
座面最大高度:1.2 mm子类别:Line Driver or Receivers
最大压摆率:1 mA最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:3.3 V
电源电压1-最大:5.5 V电源电压1-分钟:3 V
电源电压1-Nom:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mmBase Number Matches:1

SP3203EY 数据手册

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®
SP3203  
3V RS-232 Serial Transceiver with Logic Selector  
3 Driver/ 2 Receiver Architecture  
Logic selector function (VL) sets TTL  
input/output levels for mixed logic  
systems  
Meets true EIA/TIA-232-F Standards  
from a +3.0V to +5.5V power supply  
Interoperable with EIA/TIA-232 and  
adheres to EIA/TIA-562 down to a  
+2.7V power source  
Minimum 250Kbps data rate under load  
Regulated Charge Pump Yields Stable  
RS-232 Outputs Regardless of VCC  
Variations  
ESD Specifications:  
+2kV Human Body Model  
Applications  
Palmtops  
Cell phone Data Cables  
PDA's  
DESCRIPTION  
The SP3203 provides a RS-232 transceiver solution for portable and hand-held applications  
such as palmtops, PDA's and cell phones. The SP3203 uses an internal high-efficiency,  
charge-pump that requires only 0.1µF capacitors during 3.3V operation. This charge pump  
and Sipex's driver architecture allow the SP3203 to deliver compliant RS-232 performance  
from a single power supply ranging from +3.0V to +5.5V.  
The SP3203 is a 3-driver/2-receiver device, with a unique VL pin to program the TTL input  
and output logic levels to allow interoperation in mixed-logic voltage systems such as PDA's  
and cell phones. Receiver outputs will not exceed VL for VOH and transmitter input logic levels  
are scaled by the magnitude of the VL input.  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
1

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