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SP3203CY PDF预览

SP3203CY

更新时间: 2024-09-25 22:42:51
品牌 Logo 应用领域
西伯斯 - SIPEX 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
14页 121K
描述
3V RS-232 Serial Transceiver with Logic Selector

SP3203CY 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:MO-153AC, TSSOP-20Reach Compliance Code:unknown
风险等级:5.7Is Samacsys:N
差分输出:NO驱动器位数:3
输入特性:SCHMITT TRIGGER接口集成电路类型:LINE TRANSCEIVER
接口标准:EIA-232-F; TIA-232-F; V.24; V.28; EIA-562; TIA-562JESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:6.5 mm
湿度敏感等级:1功能数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:最小输出摆幅:10 V
最大输出低电流:0.0016 A封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:3.3/5 V
认证状态:Not Qualified最大接收延迟:
接收器位数:2座面最大高度:1.2 mm
子类别:Line Driver or Receivers最大压摆率:1 mA
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:3.3 V电源电压1-最大:5.5 V
电源电压1-分钟:3 V电源电压1-Nom:3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

SP3203CY 数据手册

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®
SP3203  
3V RS-232 Serial Transceiver with Logic Selector  
3 Driver/ 2 Receiver Architecture  
Logic selector function (VL) sets TTL  
input/output levels for mixed logic  
systems  
Meets true EIA/TIA-232-F Standards  
from a +3.0V to +5.5V power supply  
Interoperable with EIA/TIA-232 and  
adheres to EIA/TIA-562 down to a  
+2.7V power source  
Minimum 250Kbps data rate under load  
Regulated Charge Pump Yields Stable  
RS-232 Outputs Regardless of VCC  
Variations  
ESD Specifications:  
+2kV Human Body Model  
Applications  
Palmtops  
Cell phone Data Cables  
PDA's  
DESCRIPTION  
The SP3203 provides a RS-232 transceiver solution for portable and hand-held applications  
such as palmtops, PDA's and cell phones. The SP3203 uses an internal high-efficiency,  
charge-pump that requires only 0.1µF capacitors during 3.3V operation. This charge pump  
and Sipex's driver architecture allow the SP3203 to deliver compliant RS-232 performance  
from a single power supply ranging from +3.0V to +5.5V.  
The SP3203 is a 3-driver/2-receiver device, with a unique VL pin to program the TTL input  
and output logic levels to allow interoperation in mixed-logic voltage systems such as PDA's  
and cell phones. Receiver outputs will not exceed VL for VOH and transmitter input logic levels  
are scaled by the magnitude of the VL input.  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
1

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