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SNV54HC132J PDF预览

SNV54HC132J

更新时间: 2024-11-15 03:31:31
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
15页 514K
描述
QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

SNV54HC132J 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:CERAMIC, DIP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.28Is Samacsys:N
系列:HC/UHJESD-30 代码:R-GDIP-T14
JESD-609代码:e0长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:2/6 V
Prop。Delay @ Nom-Sup:37 ns传播延迟(tpd):186 ns
认证状态:Not Qualified施密特触发器:YES
筛选级别:38535V;38534K;883S座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

SNV54HC132J 数据手册

 浏览型号SNV54HC132J的Datasheet PDF文件第2页浏览型号SNV54HC132J的Datasheet PDF文件第3页浏览型号SNV54HC132J的Datasheet PDF文件第4页浏览型号SNV54HC132J的Datasheet PDF文件第5页浏览型号SNV54HC132J的Datasheet PDF文件第6页浏览型号SNV54HC132J的Datasheet PDF文件第7页 
ꢋ ꢌꢍꢎꢏ ꢌꢐꢑ ꢒ ꢐꢓ ꢀꢔ ꢕ ꢔꢖꢒ ꢗꢁꢍꢁ ꢎ ꢘ ꢍꢕꢒ  
SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004  
SN54HC132 . . . J OR W PACKAGE  
SN74HC132 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 20-µA Max I  
CC  
1
2
3
4
5
6
7
1A  
1B  
V
CC  
14  
13  
12  
11  
10  
9
Typical t = 14 ns  
pd  
4-mA Output Drive at 5 V  
4B  
4A  
4Y  
3B  
3A  
3Y  
1Y  
Low Input Current of 1 µA Max  
Operation From Very Slow Input  
Transitions  
2A  
2B  
2Y  
D
Temperature-Compensated Threshold  
Levels  
8
GND  
D
High Noise Immunity  
SN54HC132 . . . FK PACKAGE  
(TOP VIEW)  
D
Same Pinouts as ’HC00  
description/ordering information  
3
2
1
20 19  
18  
Each circuit functions as a NAND gate, but  
because of the Schmitt action, it has different input  
threshold levels for positive- and negative-going  
signals. The ’HC132 devices perform the Boolean  
function Y = A B or Y = A + B in positive logic.  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
3B  
These circuits are temperature compensated and  
can be triggered from the slowest of input ramps  
and still give clean jitter-free output signals.  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC132N  
SN74HC132N  
SN74HC132D  
SN74HC132DR  
SN74HC132DT  
SN74HC132NSR  
SN74HC132DBR  
SN74HC132PW  
SN74HC132PWR  
SN74HC132PWT  
SNJ54HC132J  
HC132  
SOP − NS  
HC132  
HC132  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC132  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC132J  
SNJ54HC132W  
SNJ54HC132FK  
−55°C to 125°C  
SNJ54HC132W  
SNJ54HC132FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢓ ꢜ ꢧ ꢟ ꢞꢪ ꢥꢤ ꢢꢣ ꢤꢞ ꢠꢧ ꢩꢛ ꢡꢜ ꢢ ꢢꢞ ꢚꢔ ꢑꢗ ꢐꢏ ꢱ ꢗꢇꢲꢂ ꢇꢂꢉ ꢡꢩꢩ ꢧꢡ ꢟ ꢡ ꢠꢦ ꢢꢦꢟ ꢣ ꢡ ꢟ ꢦ ꢢꢦ ꢣꢢꢦ ꢪ  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
ꢥ ꢜꢩ ꢦꢣꢣ ꢞ ꢢꢬꢦ ꢟ ꢮꢛ ꢣꢦ ꢜ ꢞꢢꢦ ꢪꢫ ꢓ ꢜ ꢡꢩ ꢩ ꢞ ꢢꢬꢦ ꢟ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢣ ꢉ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞ ꢜ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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