SNJ54S374W

更新时间： 2024-11-11 21:54:39

品牌	Logo	应用领域
德州仪器 - TI		触发器锁存器逻辑集成电路驱动
页数	文件大小	规格书
24页	638K
描述
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

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SNJ54S374W 技术参数

生命周期：	Active	零件包装代码：	DFP
包装说明：	DFP-20	针数：	20
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	6 weeks
风险等级：	5.4	Is Samacsys：	N
控制类型：	ENABLE LOW	计数方向：	UNIDIRECTIONAL
系列：	S	JESD-30 代码：	R-GDFP-F20
长度：	13.09 mm	负载电容（CL）：	15 pF
逻辑集成电路类型：	BUS DRIVER	最大频率@ Nom-Sup：	75000000 Hz
最大I（ol）：	0.02 A	位数：	8
功能数量：	1	端口数量：	2
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出特性：	3-STATE
输出极性：	TRUE	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DFP	封装等效代码：	FL20,.3
封装形状：	RECTANGULAR	封装形式：	FLATPACK
包装方法：	TUBE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	最大电源电流（ICC）：	140 mA
Prop。Delay @ Nom-Sup：	28 ns	传播延迟（tpd）：	28 ns
认证状态：	Not Qualified	筛选级别：	MIL-PRF-38535
座面最大高度：	2.54 mm	子类别：	FF/Latches
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	TTL	温度等级：	MILITARY
端子形式：	FLAT	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
触发器类型：	POSITIVE EDGE	宽度：	7.62 mm
Base Number Matches：	1

SNJ54S374W 数据手册

SN54LS373, SN54LS374, SN54S373, SN54S374,

SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

SN54LS373, SN54LS374, SN54S373,

SN54S374 . . . J OR W PACKAGE

SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE

Choice of Eight Latches or Eight D-Type

Flip-Flops in a Single Package

3-State Bus-Driving Outputs

Full Parallel Access for Loading

Buffered Control Inputs

SN74LS374 . . . DB, DW, N, OR NS PACKAGE

SN74S373 . . . DW OR N PACKAGE

(TOP VIEW)

Clock-Enable Input Has Hysteresis to

Improve Noise Rejection (’S373 and ’S374)

P-N-P Inputs Reduce DC Loading on Data

Lines (’S373 and ’S374)

description

These 8-bit registers feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The

†

GND

high-impedance

3-state

and

increased

†

Cfor’LS373and’S373;CLKfor’LS374and’S374.

high-logic-level drive provide these registers with

the capability of being connected directly to and

driving the bus lines in a bus-organized system

without need for interface or pullup components.

These devices are particularly attractive for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

SN54LS373, SN54LS374, SN54S373,

SN54S374 . . . FK PACKAGE

(TOP VIEW)

20 19

The eight latches of the ’LS373 and ’S373 are

transparent D-type latches, meaning that while

the enable (C or CLK) input is high, the Q outputs

follow the data (D) inputs. When C or CLK is taken

low, the output is latched at the level of the data

that was set up.

9 10 11 12 13

The eight flip-flops of the ’LS374 and ’S374 are

edge-triggered D-type flip-flops. On the positive

transition of the clock, the Q outputs are set to the

logic states that were set up at the D inputs.

†

Cfor’LS373and’S373;CLKfor’LS374and’S374.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design

as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered

output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic

levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly.

OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new

data can be entered, even while the outputs are off.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

unless otherwise noted. On all other products, production

testing of all parameters.

processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...24

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与SNJ54S374W相关器件

型号	品牌	获取价格	描述	数据表
SNJ54S37FK	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
SNJ54S37J	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
SNJ54S37W	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
SNJ54S381FK	TI	获取价格	ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
SNJ54S381J	TI	获取价格	ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
SNJ54S381W	TI	获取价格	ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
SNJ54S38FK	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
SNJ54S38J	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
SNJ54S38J-00	TI	获取价格	S SERIES, QUAD 2-INPUT NAND GATE, CDIP14
SNJ54S38W	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS

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