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SNJ54LVT646FK PDF预览

SNJ54LVT646FK

更新时间： 2024-11-26 15:52:27
品牌 Logo 应用领域
德州仪器 - TI 输入元件信息通信管理逻辑集成电路触发器
页数 文件大小 规格书
10页 152K
描述
3.3V ABT Octal Bus Transceivers and Registers with 3-State Outputs 28-LCCC -55 to 125

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SNJ54LVT646FK 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：CERAMIC, LCC针数：28
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.56Is Samacsys：N
其他特性：WITH DIRECTION CONTROL; WITH SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIM控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：LVT
JESD-30 代码：S-CQCC-N28长度：11.43 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.048 A位数：8
功能数量：1端口数量：2
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装等效代码：LCC28,.45SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
最大电源电流（ICC）：14 mAProp。Delay @ Nom-Sup：4.9 ns
传播延迟（tpd）：6.6 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：2.03 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：11.43 mm
Base Number Matches：1

SNJ54LVT646FK 数据手册

 浏览型号SNJ54LVT646FK的Datasheet PDF文件第2页浏览型号SNJ54LVT646FK的Datasheet PDF文件第3页浏览型号SNJ54LVT646FK的Datasheet PDF文件第4页浏览型号SNJ54LVT646FK的Datasheet PDF文件第5页浏览型号SNJ54LVT646FK的Datasheet PDF文件第6页浏览型号SNJ54LVT646FK的Datasheet PDF文件第7页 
SN54LVT646, SN74LVT646  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS140D – MAY 1992 – REVISED JULY 1995  
SN54LVT646 . . . JT OR W PACKAGE  
SN74LVT646 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static Power  
Dissipation  
CLKAB  
SAB  
DIR  
A1  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
CLKBA  
SBA  
OE  
B1  
2
)
CC  
3
Support Unregulated Battery Operation  
Down to 2.7 V  
4
A2  
5
A3  
B2  
6
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
A4  
B3  
7
= 3.3 V, T = 25°C  
CC  
A
A5  
B4  
8
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
A6  
B5  
9
A7  
A8  
GND  
B6  
B7  
B8  
10  
11  
12  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
SN54LVT646 . . . FK PACKAGE  
(TOP VIEW)  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Support Live Insertion  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and and Thin Shrink Small-Outline  
(PW) Packages, Ceramic Chip Carriers  
(FK), Ceramic Flat (W) Packages, and  
Ceramic (JT) DIPs  
4
3
2
1
28 27 26  
25  
OE  
B1  
B2  
NC  
A1  
A2  
A3  
NC  
A4  
A5  
A6  
5
24  
23  
22  
6
7
8
21 B3  
9
description  
20  
19  
10  
11  
B4  
B5  
These bus transceivers and registers are  
designed specifically for low-voltage (3.3-V) V  
12 13 14 15 16 17 18  
CC  
operation, but with the capability to provide a TTL  
interface to a 5-V system environment.  
NC – No internal connection  
The ’LVT646 consist of bus transceiver circuits,  
D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the  
input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high  
transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental  
bus-management functions that can be performed with the ′LVT646.  
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the  
transceiver mode, data present at the high-impedance port may be stored in either register or in both.  
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The  
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),  
A data may be stored in one register and/or B data may be stored in the other register.  
When an output function is disabled, the input function is still enabled and may be used to store and transmit  
data. Only one of the two buses, A or B, may be driven at a time.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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